Interrupt Table Memory Map - Freescale Semiconductor DSP56311 User Manual

22
23
11 10
T0L1
Reserved bit; read as zero; write with zero for future compatibility
Figure 4-4. Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE)
The DSP56311 has a four-level interrupt priority structure. Each interrupt has two interrupt
priority level bits (IPL[1–0]) that determine its interrupt priority level. Level 0 is the lowest
priority; Level 3 is the highest-level priority and is non-maskable. Table 4-4 defines the IPL bits.
IPL bits
xxL1 xxL0
0 0
0 1
1 0
1 1
The IPRC also selects the trigger mode of the external interrupts (
IxL2 bit is 0, the interrupt mode is level-triggered. If the value is 1, the interrupt mode is
negative-edge-triggered.
4.4.2

Interrupt Table Memory Map

Each interrupt is allocated two instructions in the interrupt table, resulting in 128 table entries for
interrupt handling. Table 4-5 shows the table entry address for each interrupt source. The
DSP56311 initialization program loads the table entry for each interrupt serviced with two
interrupt servicing instructions. In the DSP56311, only some of the 128 vector addresses are used
for specific interrupt sources. The remaining interrupt vectors are reserved and can be used for
Freescale Semiconductor
21 20 19 18
9 8 7 6
T0L0 SCL1 SCL0 S1L1
Table 4-4. Interrupt Priority Level Bits
Interrupts Enabled
No
Yes
Yes
Yes
DSP56311 User's Manual, Rev. 2
17 16 15 14
5 4 3 2
S1L0 S0L1 S0L0 HPL1
Interrupts Masked
—
0
0, 1
0, 1, 2
Configuring Interrupts
13 12
reserved
1 0
HPL0
HI08 IPL
ESSI0 IPL
ESSI1 IPL
SCI IPL
TRIPLE TIMER IPL
reserved
Interrupt Priority Level
0
1
2
3
– ). If the value of the
IRQA IRQD
4-15