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Core Configuration
This chapter presents DSP56300 core configuration details specific to the DSP56311. These
configuration details include the following:
Operating modes
Bootstrap program
Central Processor registers
— Status register (SR)
— Operating mode register (OMR)
Interrupt Priority Registers (IPRC and IPRP)
PLL control (PCTL) register
Bus Interface Unit registers
— Bus Control Register (BCR)
— DRAM Control Register (DCR)
— Address Attribute Registers (AAR[3–0])
DMA Control Registers 5–0 (DCR[5–0])
Device identification register (IDR)
JTAG identification register
JTAG boundary scan register (BSR)
For information on specific registers or modules in the DSP56300 core, refer to the DSP56300
Family Manual.
4.1 Operating Modes
The DSP56311 begins operation by leaving the Reset state and going into one of eight operating
modes. As the DSP56311 exits the Reset state, it loads the values of MODA, MODB, MODC,
and MODD into bits MA, MB, MC, and MD of the OMR. These bit settings determine the chip's
operating mode, which in turn determines the bootstrap program option the chip uses to start up.
Software can also directly set the OMR[MA–MD] bits. A jump directly to the bootstrap program
entry point ($FF0000) after the OMR bits are set causes the DSP56311 to execute the specified
bootstrap program option (except modes 0 and 8). Table 4-1 shows the DSP56311 bootstrap
operation modes, the corresponding settings of the external operational mode signal lines (the
Freescale Semiconductor
DSP56311 User's Manual, Rev. 2
4
4-1
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