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Core Configuration
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Reset
Bit Name
Number
Value
9–4
DAM[5–0]
0
3–2
DDS[1–0]
0
1–0
DSS[1–0]
0
Note:
The lowest 4 K of X data RAM and 4 K of Y data RAM are shared memory that can be
accessed by the core and the EFCOP but not by the DMA controller.
4.8 Device Identification Register (IDR)
The IDR is a read-only factory-programmed register that identifies DSP56300 family members.
It specifies the derivative number and revision number of the device. This information is used in
testing or by software. Figure 4-10 shows the contents of the IDR. Revision numbers are
assigned as follows: $0 is revision 0, $1 is revision A, and so on.
.
23
Reserved
$00
Figure 4-10. Identification Register Configuration (Revision A)
4-32
DMA Address Mode
Defines the address generation mode for the DMA transfer. These bits are encoded in two
different ways according to the D3D bit.
DMA Destination Space
Specify the memory space referenced as a destination by the DMA.
Note:
In Cache mode, a DMA to Program memory space has some limitations (as
described in the DSP56300 Family Manual in Chapter Chapter 8, Instruction
Cache , and Chapter Chapter 11, Operating Modes and Memory Spaces ).
DDS1
0
0
1
1
DMA Source Space
Specify the memory space referenced as a source by the DMA.
Note:
In Cache mode, a DMA to Program memory space has some limitations (as
described in the DSP56300 Family Manual in Chapter Chapter 8, Instruction
Cache , and Chapter Chapter 11, Operating Modes and Memory Spaces ).
DSS1
0
0
1
1
16
15
Revision Number
$0
DSP56311 User's Manual, Rev. 2
Description
DDS0
DMA Destination Memory Space
0
X Memory Space
1
Y Memory Space
0
P Memory Space
1
Reserved
DSS0
DMA Source Memory Space
0
X Memory Space
1
Y Memory Space
0
P Memory Space
1
Reserved
12
11
Derivative Number
0
$317
Freescale Semiconductor
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