External Memory Expansion Port (Port A); External Address Bus - Freescale Semiconductor DSP56311 Technical Data Manual

Signals/Connections
1.4 PLL
Signal Name Type
CLKOUT Output
PCAP Input
PINIT Input
NMI Input

1.5 External Memory Expansion Port (Port A)

Note: When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant Port A signals:
1.5.1

External Address Bus

Signal Name Type
A[0–17] Output
1-4
Table 1-5. Phase-Locked Loop Signals
State During
Reset
Chip-driven Clock Output—Provides an output clock synchronized to the internal core
clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
Note: At operating frequencies above 100 MHz, this signal produces a low-
amplitude waveform that is not usable externally by other devices. Above 100
MHz, you can use the asynchronous bus arbitration option that is enabled by
the Asynchronous Bus Arbitration Enable (ABE) bit in the Operating Mode
Register. When set, the DSP enters the Asynchronous Arbitration mode,
which eliminates the BB and BG set-up and hold time requirements with
respect to CLKOUT.
Input PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter.
Connect one capacitor terminal to PCAP and the other terminal to V
If the PLL is not used, PCAP can be tied to V
Input PLL Initial—During assertion of RESET, the value of PINIT is written into the
PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether
the PLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during normal
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI request internally synchronized to CLKOUT.
, ,
A[0–17] D[0–23] AA[0
Table 1-6. External Address Bus Signals
State During
Reset, Stop,
or Wait
Tri-stated Address Bus—When the DSP is the bus master, A[0–17] are active-high
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A[0–17] do not change state when external memory spaces are not being
accessed.
DSP56311 Technical Data, Rev. 8
Signal Description
CC
– , , , .
3] RD WR BB
Signal Description
.
CCP
, GND, or left floating.
Freescale Semiconductor