Special Cases; Dma Trigger; Triple Timer Module Programming Model; Prescaler Counter - Freescale Semiconductor DSP56311 User Manual

9.3.5 Special Cases

The following special cases apply during wait and stop state.
Timer behavior during wait. Timer clocks are active during the execution of the wait
instruction and timer activity is undisturbed. If a timer interrupt is generated, the
DSP56311 leaves the wait state and services the interrupt.
Timer behavior during stop. During execution of the stop instruction, the timer clocks are
disabled, timer activity stops, and the
that happen to the
correct operation, disable the timers before the DSP56311 is placed in stop state.

9.3.6 DMA Trigger

Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a
timer event. The timer issues a DMA trigger on every event in all modes of operation. To ensure
that all DMA triggers are serviced, provide for the preceding DMA trigger to be serviced before
the DMA channel receives the next trigger.

9.4 Triple Timer Module Programming Model

The timer programming model in Figure 9-20 shows the structure of the timer registers.

9.4.1 Prescaler Counter

The prescaler counter is a 21-bit counter that decrements on the rising edge of the prescaler input
clock. The counter is enabled when at least one of the three timers is enabled (that is, one or more
of the timer enable bits are set) and is using the prescaler output as its source (that is, one or more
of the PCE bits are set).
Freescale Semiconductor
TIO
signals are ignored when the DSP56311 is in stop state. To ensure
TIO
DSP56311 User's Manual, Rev. 2
Triple Timer Module Programming Model
signals are disconnected. Any external changes
9-21