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•
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This
recommendation particularly applies to the address and data buses as well as the
, and
pins. Maximum PCB trace lengths on the order of 6 inches are recommended.
TA
BG
•
Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate
capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the
•
All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with
internal pull-up resistors (
•
Take special care to minimize noise levels on the
•
The following pins must be asserted during power-up:
supplied before deassertion of
other "required
RESET
uninitialized state that may result in significant power consumption and heat-up. Designs should minimize
this condition to the shortest possible duration.
•
Ensure that during power-up, and throughout the DSP56311 operation, V
the V
voltage level.
CC
•
If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due
to synchronous operation of the devices.
•
The Port A data bus (
last output value even when the internal signal is tri-stated. Typically, no pull-up or pull-down resistors
should be used with these signal lines. However, if the DSP is connected to a device that requires pull-up
resistors (such as an MPC8260), the recommended resistor value is 10 KΩ or less. If more than one DSP
must be connected in parallel to the other device, the pull-up resistor value requirement changes as
follows:
— 2 DSPs = 7 KΩ or less
— 3 DSPs = 4 KΩ or less
— 4 DSPs = 3 KΩ or less
— 5 DSPs = 2 KΩ or less
— 6 DSPs = 1.5 KΩ or less
4.3 Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption
are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is
charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by this
formula:
Equation 3:
I
Where:
C
=
V
=
f
=
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33
MHz), the current consumption is expressed in Equation 4.
Freescale Semiconductor
and
circuits.
V
GND
CC
,
,
).
TRST
TMS
DE
. If the V
RESET
duration" conditions are met (see Table 2-7), the device circuitry can be in an
), HI08, ESSI0, ESSI1, SCI, and timers all use internal keepers to maintain the
D[0–23]
×
×
=
C
V
f
node/pin capacitance
voltage swing
frequency of node/pin toggle
Example 4-1. Current Consumption
DSP56311 Technical Data, Rev. 8
Power Consumption Considerations
,
, and
V
GND
GND
CCP
P
P1
and
RESET
TRST
reaches the required level before EXTAL is stable or
CC
,
,
IRQA
IRQB
IRQC
pins.
. A stable
signal should be
EXTAL
is always higher or equal to
CCQH
,
,
IRQD
4-3
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