Programming Reference; Internal I/O Memory Map - Freescale Semiconductor DSP56311 User Manual

Programming Reference

Table B-1. Guide to Programming Sheets (Continued)
HI08 Figure B-10, Host Transmit Data Register
Figure B-11, Host Base Address and Host Port Control Registers
Figure B-12, Host Control Register
Figure B-13, Interrupt Control and Command Vector Registers
Figure B-14, Interrupt Vector and Host Transmit Data Registers
ESSI Figure B-15, ESSI Control Register A (CRA)
Figure B-16, ESSI Control Register B (CRB)
Figure B-17, ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)
SCI Figure B-18, SCI Control Register (SCR)
Figure B-19, SCI Clock Control Registers (SCCR)
Timers Figure B-20, Timer Prescaler Load Register (TPLR)
Figure B-21, Timer Control/Status Register (TCSR)
Figure B-22, Timer Load, Compare, and Count Registers (TLR, TCPR, TCR)
GPIO Figure B-23, Host Data Direction and Host Data Registers (HDDR, HDR)
Figure B-24, Port C Registers (PCRC, PRRC, PDRC)
Figure B-25, Port D Registers (PCRD, PRRD, PDRD)
Figure B-26, Port E Registers (PCRE, PRRE, PDRE)
Figure B-27, EFCOP Counter and Control Status Registers (FCNT and FCSR)
EFCOP
Figure B-28, EFCOP FACR, FDBA, FCBA, and FDCH Registers
B.1 Internal I/O Memory Map
Table B-2. Internal I/O Memory Map (X Data Memory)
Peripheral 16-Bit Address
IPR
PLL
OnCE
BIU
B-2
24-Bit Address
$FFFF $FFFFFF
$FFFE $FFFFFE
$FFFD $FFFFFD
$FFFC $FFFFFC
$FFFB $FFFFFB
$FFFA $FFFFFA
$FFF9 $FFFFF9
$FFF8 $FFFFF8
$FFF7 $FFFFF7
$FFF6 $FFFFF6
$FFF5 $FFFFF5
DSP56311 User's Manual, Rev. 2
Register Name
Interrupt Priority Register Core (IPRC)
Interrupt Priority Register Peripheral (IPRP)
PLL Control Register (PCTL)
OnCE GDB Register (OGDB)
Bus Control Register (BCR)
DRAM Control Register (DCR)
Address Attribute Register 0 (AAR0)
Address Attribute Register 1 (AAR1)
Address Attribute Register 2 (AAR2)
Address Attribute Register 3 (AAR3)
ID Register (IDR)
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