Programming Sheets - Freescale Semiconductor DSP56311 User Manual

24-bit digital signal processor (dsp)
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Application:
Central Processor
Address Attribute Priority Disable, Bit 14
0 = Priority mechanism enabled
1 = Priority mechanism disabled
Address Trace Enable, Bit 15
0 = Address Trace mode disabled
1 = Address Trace mode enabled
*valid for 100 MHz or less only
Stack Extension X Y Select, Bit 16
0 = Mapped to X memory
1 = Mapped to Y memory
Stack Extension Underflow Flag, Bit 17
0 = No stack underflow
1 = Stack underflow
Stack Extension Overflow Flag, Bit 18
0 = No stack overflow
1 = Stack overflow
Stack Extension Wrap Flag, Bit 19
0 = No stack extension wrap
1 = Stack extension wrap (sticky bit)
Stack Extension Enable, Bit 20
0 = Stack extension disabled
1 = Stack extension enabled
Memory Switch Configuration, Bits 22 – 21
Refer to the memory maps in Chapter 3 for
details.
23
22
21 20
*
MSW1
MSW0
SEN
0
Operating Mode Register
Reset = $00030X; X = latched from levels on Mode pins
Freescale Semiconductor
Asynchronous Bus Arbitration Enable, Bit 13
0 = Synchronization disabled
1 = Synchronization enabled
19 18 17 16
15 14 13 12 11 10 9
WRP EOV
EUN
XYS
ATE
APD ABE
Figure B-2. Operating Mode Register (OMR)
DSP56311 User's Manual, Rev. 2
External Bus Disable, Bit 4
0 = Enables external bus
1 = Disables external bus
Stop Delay Mode, Bit 6
0 = Delay is 128K clock cycles
1 = Delay is 16 clock cycless
Memory Switch Mode, Bit 7
0 = Memory switching disabled
1 = Memory switching enabled
Core-DMA Priority, Bits 9–8
CPD[1:0]
00
Compare SR[CP] to
active DMA channel
priority
01
DMA has higher
priority than core
10
DMA has same
priority as core
11
DMA has lower
priority than core
Cache Burst Mode Enable, Bit 10
0 = Burst Mode disabled
1 = Burst Mode enabled
TA Synchronize Select, Bit 11
0 = Not synchronized
1 = Synchronized
Bus Release Timing, Bit 12
0 = Fast Bus Release mode
1 = Slow Bus Release mode
8
7
BRT TAS
BE
CPD1
CPD0
MS
*

Programming Sheets

Date:
Programmer:
Sheet 2 of 2
Chip Operating Mode, Bits 3–0
Refer to the operating modes
table in Chapter 4.
Description
6
5
4
3
2
1
0
*
SD
EBD
MD
MC MB
MA
0
= Reserved, Program as 0
B-13

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