Pll Performance Issues - Freescale Semiconductor DSP56311 Technical Data Manual

Design Considerations
Equation 4:
The maximum internal current (I
case operation conditions—not necessarily a real application case. The typical internal current (I
reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for
applications that require very low current consumption:
Set the EBD bit when you are not accessing external memory.
1.
Minimize external memory accesses, and use internal memory accesses.
2.
Minimize the number of pins that are switching.
3.
Minimize the capacitive load on the pins.
4.
Connect the unused inputs to pull-up or pull-down resistors.
5.
Disable unused peripherals.
6.
Disable unused pin activity (for example, CLKOUT, XTAL).
7.
One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize
specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark
power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current
measurements, and the following equation to derive the current-per-MIPS value.
⁄
Equation 5:
Where:
I =
typF2
I =
typF1
F2 =
F1 =
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The
degree of difference between F1 and F2 determines the amount of precision with which the current rating
can be determined for an application.

4.4 PLL Performance Issues

The following explanations should be considered as general observations on expected PLL behavior. There is no
test that replicates these exact numbers. These observations were measured on a limited number of parts and were
not verified over the entire temperature and voltage ranges.
4.4.1 Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of
given capacitive load on
CLKOUT
2, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz and the MF ≤4, this skew is
greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10
and input frequencies greater than 10 MHz, this skew is between − 1.4 ns and +3.2 ns.
4-4
– 12
× × × ×
I = 50 10 3.3 33 10
max) value reflects the typical possible switching of the internal buses on best-
CCI
⁄ (
MIPS = I MHz = I –
typF2
current at F2
current at F1
high frequency (any specified operating frequency)
low frequency (any specified operating frequency lower than F2)
, over the entire process, temperature and voltage ranges. As defined in Figure 2-
DSP56311 Technical Data, Rev. 8
6
= 5.48 mA
) ⁄ (
I F2 F1 –
typF1
) value
CCItyp
and for a
EXTAL CLKOUT
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