Table of Contents
Advertisement
nop
jmp stop_label
org x:SRC_ADDRS
INCLUDE 'input.asm'
org y:FCBA_ADDRS
INCLUDE 'coefs.asm'
10.3.6.1.3 DMA Input/Interrupt Output
The different stages of DMA input and interrupt output are as follows:
1.
Set up:
• Set the filter count register (FCNT) to the length of the filter coefficients –1 (that is,
N – 1).
• Set the Data and Coefficient Base Address pointers (FDBA, FCBA).
• Set the operation mode (FCSR[5:4] = FOM[00],).
• Set Initialization mode (FCSR[7] = FPRC = 0).
• Set Filter Data Output Interrupt Enable FSCR[11]=FDOIE=1.
• Set DMA register with DMA input as per channel 0 in Section 10.3.6.1.1.
Initialization:
2.
• Enable interrupts in the Interrupt Priority Register IPRP[10:11]=E0L=11.
• Enable interrupts in the Status Register SR[8:9]=00.
• Enable EFCOP FCSR[0]=FEN=1.
• Enable the DMA input channel, DCR0[23]=DE=1.
Processing:
3.
• Whenever the Input Data Buffer (FDIR) is empty (that is, FDIBE = 1), the EFCOP
triggers DMA, which loads the next input into the FDIR.
• Compute F(n); the result is stored in FDOR; The core is interrupted when FDOBF
is set and stores the data in memory.
Example 10-3. Real FIR Filter DMA Input/Interrupt Output
INCLUDE 'ioequ.asm'
;;******************************************************************
; equates
;;******************************************************************
Startequ$00100; main program starting address
FCON equ
$801 ; EFCOP FSCR register contents:
Freescale Semiconductor
DSP56311 Reference Manual, Rev. 2
EFCOP Operation
10-21
Advertisement
Table of Contents
