Sci Clock Control Register (Sccr) - Freescale Semiconductor DSP56311 User Manual

8.6.3 SCI Clock Control Register (SCCR)

The SCCR is a read/write register that controls the selection of clock modes and baud rates for
the transmit and receive sections of the SCI interface. The SCCR is cleared by a hardware
signal.
23 22
15 14
TCM RCM
7 6
CD7 CD6
Reserved. Read as 0. Write to 0 for future compatibility.
Table 8-5. SCI Clock Control Register (SCCR) Bit Definitions
Bit Reset
Bit Name
Number Value
23–16
15 TCM
14 RCM
13 SCP
12 COD
11–0 CD[11–0]
Freescale Semiconductor
21
13
SCP COD
5
CD5 CD4
Figure 8-4. SCI Clock Control Register (SCCR)
0 Reserved. Write to 0 for future compatibility.
0 Transmit Clock Source
Selects whether an internal or external clock is used for the transmitter. If TCM is cleared,
the internal clock is used. If TCM is set, the external clock (from the SCLK signal) is used.
0 Receive Clock Mode Source
Selects whether an internal or external clock is used for the receiver. If RCM is cleared, the
internal clock is used. If RCM is set, the external clock (from the SCLK signal) is used.
TCM RCM TX Clock
0 0 Internal
0 1 Internal
1 0 External
1 1 External
0 Clock Prescaler
Selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for the clock
divider. The output of the prescaler is further divided by 2 to form the SCI clock.
0 Clock Out Divider
The clock output divider is controlled by COD and the SCI mode. If the SCI mode is
synchronous, the output divider is fixed at divide by 2. If the SCI mode is asynchronous,
either:
• If COD is cleared and SCLK is an output (that is, TCM and RCM are both cleared), then
the SCI clock is divided by 16 before being output to the SCLK signal. Thus, the SCLK
×
output is a 1 clock.
• If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK signal.
Thus, the SCLK output is a 16
0 Clock Divider
Specifies the divide ratio of the prescale divider in the SCI clock generator. A divide ratio
from 1 to 4096 (CD[11–0] = $000 to $FFF) can be selected.
DSP56311 User's Manual, Rev. 2
20 19
12 11
CD11
4 3
CD3
Description
RX Clock SCLK
Internal Output
External Input
Internal Input
External Input
×
baud clock.
SCI Programming Model
18 17
10 9
CD10 CD9
2 1
CD2 CD1
Mode
Synchronous/asynchronous
Asynchronous only
Asynchronous only
Synchronous/asynchronous
RESET
16
8
CD8
0
CD0
8-17