Bus Interface Unit (Biu) Registers; Bus Control Register - Freescale Semiconductor DSP56311 User Manual

Core Configuration
Table 4-7. PLL Control Register (PCTL) Bit Definitions (Continued)
Bit Number Bit Name
18 PEN
17 PSTP
16 XTLD
15 XTLR
14–12 DF[2–0]
11–0 MF[11–0]

4.6 Bus Interface Unit (BIU) Registers

The three Bus Interface Unit (BIU) registers configure the external memory expansion port (Port
A). They include the following:
Bus Control Register (BCR)
DRAM Control Register (DCR)
Address Attribute Registers (AAR[3–0])
To use Port A correctly, configure these registers as part of the bootstrap process. The following
subsections describe these registers.
4.6.1

Bus Control Register

The Bus Control Register (BCR), depicted in Figure 4-6, is a read/write register that controls the
external bus activity and Bus Interface Unit (BIU) operation. All BCR bits except bit 21, BBS,
are read/write bits. The BCR bits are defined in Table 4-8.
4-20
Reset Value
Set to PINIT PLL Enable
input value Enables PLL operation.
0 PLL Stop State
Controls PLL and on-chip crystal oscillator behavior during the stop
processing state.
0 XTAL Disable
Controls the on-chip crystal oscillator XTAL output. The XTLD bit is cleared
during DSP56311 hardware reset, so the XTAL output signal is active,
permitting normal operation of the crystal oscillator.
0 Crystal Range
Controls the on-chip crystal oscillator transconductance. The XTLR bit is
cleared (0) during hardware reset in the DSP56303.
0 Division Factor
Define the DF of the low-power divider. These bits specify the DF as a power
of two in the range from 2
0 PLL Multiplication Factor
Define the multiplication factor that is applied to the PLL input frequency. The
MF bits are cleared during DSP56311 hardware reset and thus correspond to
an MF of one.
DSP56311 User's Manual, Rev. 2
Description
0 7
to 2 .
Freescale Semiconductor