Host Status Register (Hsr) - Freescale Semiconductor DSP56311 User Manual

Table 6-8. Host Control Register (HCR) Bit Definitions
Bit Number Bit Name
2 HCIE
1 HTIE
0 HRIE

6.6.2 Host Status Register (HSR)

The HSR is a 16-bit read-only status register by which the DSP reads the HI08 status and flags.
The host processor cannot access it directly. The initialization values for the HSR bits are
discussed in Section 6.6.9, DSP-Side Registers After Reset, on page 6-20.
15 14 13
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 6-7. Host Status Register (HSR) (X:$FFFFC3)
Bit Number Bit Name
15–5
Freescale Semiconductor
Reset Value
0 Host Command Interrupt Enable
Generates a host command interrupt request if the host command pending
(HCP) status bit in the HSR is set. If HCIE is cleared, HCP interrupts are
disabled. The interrupt address is determined by the host command vector
register (CVR).
NOTE: If more than one interrupt request source is asserted and enabled
(for example, HRDF is set, HCP is set, HRIE is set, and HCIE is set), the
HI08 generates interrupt requests according to priorities shown here. The bit
value is indeterminate after an individual reset.
0 Host Transmit Interrupt Enable
Generates a host transmit data interrupt request if the host transmit data
empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is
transferred from the HTX to the RXH, RXM, or RXL registers. If HTIE is
cleared, HTDE interrupts are disabled. The bit value is indeterminate after
an individual reset.
0 Host Receive Interrupt Enable
Generates a host receive data interrupt request if the host receive data full
(HRDF) bit in the host status register (HSR, Bit 0) is set. The HRDF bit is set
when data is transferred to the HRX from the TXH, TXM, or TXL registers. If
HRIE is cleared, HRDF interrupts are disabled. The bit value is
indeterminate after an individual reset.
12 11 10 9
Table 6-9. Host Status Register (HSR) Bit Definitions
Reset Value
0 Reserved. Write to 0 for future compatibility.
DSP56311 User's Manual, Rev. 2
Description
Priority
Highest
Lowest
8 7 6 5
HF1
Description
DSP Core Programming Model
Interrupt Source
Host Command (HCP = 1)
Transmit Data (HTDE = 1)
Receive Data (HRDF = 1)
4 3 2 1
HF0 HCP HTDE HRDF
0
6-13