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Memory Configuration
Because an interrupt could cause the DSP to fetch instructions out of sequence and might violate
the switch condition, special care should be taken in relation to the interrupt vector routines.
Pay special attention when executing a memory switch routine using
the OnCE port. Running the switch routine in trace mode, for
example, can cause the switch to complete after the MS/MSW bits
change while the DSP is in Debug mode. As a result, subsequent
instructions may be fetched according to the new memory
configuration (after the switch) and thus may execute improperly.
3.5 Sixteen-Bit Compatibility Mode Configuration
The sixteen-bit compatibility (SC) mode allows the DSP56311 to use DSP56000 object code
without change. The SC bit (Bit 13 in the SR) is used to switch from the default 24-bit mode to
this special 16-bit mode. SC is cleared by reset. You must set this bit to select the SC mode. The
address ranges described in the previous sections apply in the SC mode with regard to the
reallocation of X and Y data memory to program memory in MS mode, but the maximum
addressing ranges are limited to $FFFF, and all data and program code are 16 bits wide.
3.6 Memory Maps
The following figures illustrate each of the memory space and RAM configurations defined by
the settings of the MS (and MSW[1:0]), CE, and SC bits. The figures show the configuration and
describe the bit settings, memory sizes, and memory locations.
3-8
CAUTION
DSP56311 User's Manual, Rev. 2
Freescale Semiconductor
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