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DSP56311 Overview
Direct memory access (DMA)
— Six DMA channels supporting internal and external accesses
— One-, two-, and three- dimensional transfers (including circular buffering)
— End-of-block-transfer interrupts
— Triggering from interrupt lines and all peripherals
Phase lock loop (PLL)
— Allows change of low power Divide Factor (DF) without loss of lock
— Output clock with skew elimination
Hardware debugging support
— On-chip emulation (OnCE) module
— Joint Test Action Group (JTAG) Test Access Port (TAP)
— Address Trace mode reflects internal program RAM accesses at the external port
Reduced power dissipation
— Very low-power CMOS design
— Wait and stop low-power standby modes
— Fully-static design specified to operate down to 0 Hz (dc)
— Optimized power-management circuitry (instruction-dependent, peripheral-dependent,
and mode-dependent)
1.6 DSP56300 Core Functional Blocks
The functional blocks of the DSP56300 core are:
Data arithmetic logic unit (ALU)
Address generation unit
Program control unit
PLL and clock oscillator
JTAG TAP and OnCE module
Memory
In addition, the DSP56311 provides a set of internal peripherals, discussed in
Section 1.9, Peripherals, on page 1-12.
1.6.1 Data ALU
The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
Fully pipelined 24 × 24-bit parallel multiplier-accumulator
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit
stream generation and parsing)
1-6
DSP56311 User's Manual, Rev. 2
Freescale Semiconductor
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