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An optional high-speed (OHS) memory board. The PICE system provides up to 256K
bytes of additional programmable wait-state RAM for each emulator. With the PICE sys
tem, you can specify zero wait-states for real-time emulation and simulate slow memories
by inserting up to 15 wait states.
•
Program memory mapping to high-speed (HS) memory (up to 32K-bytes) on the system
map-I/O board, to OHS memory, or to host development system memory. [There is no
mapping to IBM PC/AT or PC/XT host memory.]
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Multiprocessor debugging. The PICE system can control up to four emulators
simultaneously.
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Coprocessor support, which provides debugging support for the 8087 numeric coproces
sor and the 80287 numeric processor extension.
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Emulation flexibility. The iAPX 86/88 and 186/188 emulation personality modules (also
called probes) each emulates two separate microprocessors. To change microprocessors,
you need only change the personality module CPU chip and jumpers on the buffer and
personality boards.
Probe CPU chips must be provided by Intel. All probes use either bond-out chips or
specially tested microprocessors.
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Symbolic debugging support for programs written in assembly language, PL/M, C,
Pascal, and FORTRAN by both PSCOPE-86 and the PICE system command language.
With the symbolic debugging capabilities you can access variables and memory locations
with user-defined names.
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Two programmable event machines that allow break and trace on simple and complex
event sequences.
•
A real-time trace buffer that displays trace information in either a disassembled-instruction
format or a microprocessor bus-cycle format.
The Base C onfiguration of the PICE™ System
Figure 1-2 shows a basic single-chassis PICE system. The base configuration is readily ex
pandable to include a number of PICE system options.
The base configuration of the PICE system contains the following hardware:
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The host interface board, which resides in the host development system and handles com
munication between the host development system and the PICE instrumentation chassis.
•
The PICE instrumentation chassis, which contains the communications board and pro
vides slots for up to four PICE system boards. The communications board connects to the
host interface board. The chassis slots also hold the map-I/O board and the break/trace
board. •
•
The map-I/O board, which contains high-speed RAM and the memory map. There are
32K bytes of high-speed RAM available to user programs through the memory map. The
1-4
NOTE
PICE™ System Overview
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