Deadlock Configuration; Table 3-32 Pci Configuration Address Register For Direct Master-To-Pci Io/Cfg - Intel i960 Series User Manual

Table 3-32. PCI Configuration Address Register for Direct Master-to-PCI IO/CFG
Field
Configuration Type:
1:0
00=Type 0
01=Type 1
7:2 Register Number
10:8 Function Number
15:11 Device Number
23:16 Bus Number
30:24 Reserved
Configuration Enable. Parameters in this table are used to generate the
PCI configuration address.
0 - do not allow Local-to-PCI I/O accesses to be converted to a PCI config-
31
uration cycle.
1 - allow Local-to-PCI I/O accesses to be converted to a PCI configuration
cycle.
3.12.3

Deadlock Configuration

When the PCI-SDK Platform is configured to act as a PCI bus master, a possible deadlock condition
exists. If a PCI master requests the local bus on the PCI-SDK Platform at the same time that the PCI-
SDK Platform is attempting to access the local processor's host bus, both requests are answered with a
RETRY signal. RETRY, however, does not cause either processor to release its local bus — so neither
request can be completed — and the system will deadlock.
There are two possible resolutions to this problem. The first, and simplest, is to design a system such
that memory is shared only on the host or PCI-SDK Platform, and never both. In such a system, only
one local bus is being shared by more than one processor, thereby avoiding the deadlock situation.
The second solution is somewhat more involved, and can be implemented only on the Cx and Hx
processors. This solution involves a hardware detection of the deadlock condition. Once the deadlock
has occurred, a method of signalling the i960 processor to abort its current request and relinquish its
local bus is needed. This allows the host processor's transaction to complete.
The Cx and Hx processors possess a BACKOFF pin which serves this purpose. On a PCI-SDK Platform
equipped with a Cx or Hx CPU module, the PCI 9060 asserts BACKOFF to the processor in the event of
a deadlock. The processor then relinquishes its local bus, and the host's transaction completes.
The Kx, Sx, and Jx, however, lack such a feature. Instead, logic has been included to assert a false
READY signal to these processors. This results in erroneous data being returned in the case of a read,
but the processor will terminate the cycle, allowing the host processor access to its local bus. Some
method of notifying the i960 processor that this error has occurred is needed, otherwise the erroneous
data or incomplete write goes undetected by the i960 processor.
Description
HARDWARE REFERENCE
Value after Reset
Read Write
(Cold PC Reset)
Yes Yes 0
Yes Yes 0
Yes Yes 0
Yes Yes 0
Yes Yes 0
Yes Yes 0
Yes Yes 0
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