Intel altera Agilex 3 Series User Manual
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Intel altera Agilex 3 Series User Manual

Intel altera Agilex 3 Series User Manual

Fpgas and socs clocking and pll
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Altera
Design Hub
Clocking and PLL User Guide
™
Agilex
3 FPGAs and SoCs
®
Updated for Quartus
Online Version
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Prime Design Suite: 25.1
847921
2025.04.07

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Summary of Contents for Intel altera Agilex 3 Series

  • Page 1 Explore more resources ® Altera Design Hub Clocking and PLL User Guide ™ Agilex 3 FPGAs and SoCs ® Updated for Quartus Prime Design Suite: 25.1 847921 Online Version Send Feedback 2025.04.07...

  • Page 2: Table Of Contents

    Contents Contents ™ 1. Agilex 3 Clocking and PLL Overview................4 1.1. Clock Networks Overview..................4 1.2. PLLs Overview.......................4 2. Agilex 3 Clocking and PLL Architecture and Features............5 2.1. Clock Networks Architecture and Features..............5 2.1.1. Clock Network Architecture................. 5 2.1.2. Clock Resources..................7 2.1.3.
  • Page 3 Contents 6. I/O PLL Reconfiguration....................42 6.1. Release Information for EMIF Calibration FPGA IP.............42 6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP......43 6.2.1. Setting Up the IOPLL FPGA IP..............43 6.2.2. Setting Up the EMIF Calibration FPGA IP............. 44 6.2.3.

  • Page 4: Agilex ™ 3 Clocking And Pll Overview

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 5: Agilex 3 Clocking And Pll Architecture And Features

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 6 2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 2.1.1.2. Clock Sectors Each clock sector has a dedicated sector clock (SCLK) network and a row clock network that can be accessed by the programmable clock routing. On each side of the clock sector, there is a channel that contains 64 unidirectional wires in bidirectional pairs, where only one wire in each pair can be used at one time.

  • Page 7: Clock Resources

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 skew for crossing clock networks using different clock tree branches grows, potentially degrading the maximum performance. For very high-speed clock signals, it is advantageous to follow these guidelines: •...

  • Page 8: Clock Control Features

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 For more information about the clock input pins connections, refer to the pin connection guidelines. 2.1.3. Clock Control Features The following figure shows a high-level description of the Agilex 3 clock control features—clock gating and clock divider.

  • Page 9: Clock Divider

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Altera recommends using the clock gate with a negative latch to provide glitch free gating on the output clock signal ( ). The clock gate captures the enable signal outclk ) on the next rising edge of the input clock signal ( ).

  • Page 10: Plls Architecture And Features

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 The clock divider has three outputs as follows: • First output—passes through the input clock. • Second output—divides the input clock by two. • Third output—divides the input clock by four. These three clock outputs are edge-aligned at the output of the clock divider.
  • Page 11 2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Feature I/O Bank I/O PLL Fabric-Feeding I/O Source synchronous compensation Direct compensation Normal compensation Zero-delay buffer compensation — External feedback compensation — LVDS compensation — Voltage-controlled oscillator (VCO) output drives the DPA clock —...

  • Page 12: Pll Usage

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 2.2.2. PLL Usage I/O bank I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use both the I/O bank I/O PLLs and fabric-feeding I/O PLLs to: •...

  • Page 13: Pll Architecture

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Figure 9. Fabric-feeding I/O PLL location in HVIO Block HVIO Block HVIO-Bank HVIO-Bank Fabric Feeding I/O PLL 2.2.4. PLL Architecture Figure 10. I/O Bank I/O PLL High-Level Block Diagram for Agilex 3 Devices To DPA Block For single-ended clock inputs, only the CLKp and CLKn pins have dedicated connection to the PLL.

  • Page 14: Pll Control Signals

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Note: 1. The dedicated clock inputs can feed only one PLL through the dedicated clock path. To feed the second PLL, the clock must be routed onto a global clock network.

  • Page 15: Pll Feedback Modes

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 2.2.6. PLL Feedback Modes PLL feedback modes compensate for clock network delays to align the rising edge of the output clock with the rising edge of the PLL's reference clock. Select the appropriate type of compensation for the timing critical clock path in your design.

  • Page 16: Lvds Compensation Mode

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Figure 12. Example of Phase Relationship Between the PLL Clocks in Direct Mode Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port The PLL clock outputs lag the PLL input clocks depending on routing...

  • Page 17: Normal Compensation Mode

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 2.2.6.3. Source Synchronous Compensation Mode If the data and clock signals arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays if you use the same I/O standard.

  • Page 18: Zero-Delay Buffer Mode

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Figure 15. Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port Dedicated PLL Clock Outputs The external clock output can...

  • Page 19: External Feedback Mode

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Figure 16. Example of Phase Relationship Between the PLL Clocks in ZDB Mode Phase Aligned PLL Reference Clock at the Input Pin The internal PLL clock PLL Clock at the output can lead or lag Register Clock Port the external PLL clock...

  • Page 20: Clock Multiplication And Division

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Figure 17. Example of Phase Relationship Between the PLL Clocks in EFB Mode Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port The PLL clock outputs can lead or lag the fbin clock input.

  • Page 21: Programmable Phase Shift

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 software sets the VCO frequency to 1.1 GHz (the least common multiple of 55 MHz and 100 MHz within the VCO operating frequency range). Then the post-scale counters, , scale down the VCO frequency for each output port.

  • Page 22: Pll Input Clock Switchover

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 • Cascading via dedicated cascade path—upstream I/O PLL and downstream I/O PLL must be in the same I/O column and are placed adjacently. • Cascading via core clock fabric—no restriction on locations of upstream and downstream I/O PLL.

  • Page 23: Automatic Switchover

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Agilex 3 I/O PLLs support the following clock switchover modes: • Automatic switchover—the clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to clock.
  • Page 24 2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 signal indicates which of the two clock inputs ( activeclock inclk0 inclk1 is being selected as the reference clock to the I/O PLL. When the frequency difference between the two clock inputs is more than 20%, the signal is the only activeclock valid status signal.

  • Page 25: Automatic Switchover With Manual Override

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Figure 21. Automatic Switchover After Loss of Clock Detection This figure shows an example waveform of the switchover feature in automatic switchover mode. In this example, the signal is held low. After the signal is held low for approximately two clock cycles, inclk0 inclk0...

  • Page 26: Manual Control

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Figure 22. Clock Switchover Using the (Manual) Control extswitch This figure shows a clock switchover waveform controlled by the signal. In this case, both clock extswitch sources are functional and is selected as the reference clock.

  • Page 27: Pll Reconfiguration And Dynamic Phase Shift

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 Figure 23. Manual Clock Switchover Circuitry in Agilex 3 I/O PLLs extswitch Clock Switch Control Logic inclk0 N Counter inclk1 muxout refclk fbclk You can delay the clock switchover action by specifying the switchover delay in the IP cores for the I/O PLL.

  • Page 28: User Calibration

    2. Agilex 3 Clocking and PLL Architecture and Features 847921 | 2025.04.07 2.2.13.2. User Calibration The I/O PLL must be recalibrated for any of the following conditions after device power • Dynamic I/O PLL reconfiguration that changes the counter settings is performed.

  • Page 29: Agilex 3 Clocking And Pll Design Considerations

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 30: Guidelines: Timing Closure

    3. Agilex 3 Clocking and PLL Design Considerations 847921 | 2025.04.07 3.2. Guidelines: Timing Closure For timing closure, refer to the following guidelines: • Reconfiguring a PLL's counter and loop filter settings changes both the output frequency and the clock uncertainty of that I/O PLL. Dynamic phase shift only affects the output clock phase.

  • Page 31: Ip Constraints

    3. Agilex 3 Clocking and PLL Design Considerations 847921 | 2025.04.07 3.6. IP Constraints To implement the IOPLL IP, you must adhere to the following constraints: • Any SDC design constraints referring to the I/O PLL clocks must be listed after the SDC constraints for the IOPLL IP.

  • Page 32: Clock Control Altera ™ Fpga Ip Core

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 33: Clock Control Altera Fpga Ip Ports And Signals

    ™ 4. Clock Control Altera FPGA IP Core 847921 | 2025.04.07 Parameter Value Description Clock multiplexing in Agilex 3 devices is implemented using soft logic in the core. Ensure glitch free clock On or Off Turn on this option to implement a glitch-free switchover in soft logic switchover when you use multiple clock inputs.
  • Page 34 ™ 4. Clock Control Altera FPGA IP Core 847921 | 2025.04.07 Port Name Description Output of the Clock Control IP when Clock Divider option is not selected. outclk Clock enable of the clock gate block. This signal is active-high. Outputs of the Clock Control IP when the Clock Divider option is selected. The exact clock_div1x combination of ports exposed depends on the value specified for the Clock Divider Output clock_div2x...

  • Page 35: Iopll Fpga Ip

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 36: Iopll Fpga Ip Parameters

    5. IOPLL FPGA IP 847921 | 2025.04.07 5.2. IOPLL FPGA IP Parameters The IOPLL FPGA IP is available under the PLL category of the IP Catalog. 5.2.1. IOPLL IP Parameters - PLL Tab Table 8. IOPLL IP Parameters - PLL Tab for Agilex 3 Devices Parameter Value Description...
  • Page 37 5. IOPLL FPGA IP 847921 | 2025.04.07 Parameter Value Description Use Non-dedicated Feedback On or Off Turn on to conserve clock resources and improve timing analysis. Path However, this feature creates frequency limitations and disables phase shift. Number of Clocks 1–7 (fabric- Specifies the number of output clocks required for each device in the feeding), 1–4...

  • Page 38: Iopll Ip Parameters - Settings Tab

    5. IOPLL FPGA IP 847921 | 2025.04.07 5.2.2. IOPLL IP Parameters - Settings Tab Table 9. IOPLL IP Parameters - Settings Tab for Agilex 3 Devices Parameter Value Description PLL Auto Reset On or Off Automatically self-resets the PLL on loss of lock. Create a second input clk On or Off Turn on to provide a backup clock attached to your PLL that can...

  • Page 39: Iopll Ip Parameters - Cascading Tab

    5. IOPLL FPGA IP 847921 | 2025.04.07 5.2.3. IOPLL IP Parameters - Cascading Tab Table 10. IOPLL IP Parameters - Cascading Tab Parameter Value Description Connect to an upstream PLL On or Off Turn on to create an input port to enable destination (downstream) through Core clock Network PLL power-up calibration.

  • Page 40: Iopll Ip Ports And Signals

    5. IOPLL FPGA IP 847921 | 2025.04.07 Output Clock C Counter outclk3 outclk4 outclk5 outclk6 5.3. IOPLL IP Ports and Signals Table 13. IOPLL IP Ports for Agilex 3 Devices Port Name Type Condition Description Input Required The reference clock source that drives the I/O PLL. refclk Input Required...

  • Page 41: Enables This Parameter In Case The Pll Feeds An Lvds

    5. IOPLL FPGA IP 847921 | 2025.04.07 Port Name Type Condition Description Input Optional This is an input port for the downstream I/O PLL. Connect permit_cal this port to the output port of the permit_cal locked upstream I/O PLL. Connecting this port permit_cal ensures that the cascaded I/O PLLs are calibrated in the...

  • Page 42: I/O Pll Reconfiguration

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 43: Implementing Hsio I/O Pll Reconfiguration Using Emif Calibration Ip

    6. I/O PLL Reconfiguration 847921 | 2025.04.07 Table 14. EMIF Calibration FPGA IP Current Release Information Item Description IP Version 2.1.0 Version 25.1 Release Date 2025.04.07 Related Information EMIF Calibration FPGA IP Release Notes 6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP The EMIF Calibration IP is capable of three functional reconfigurations.

  • Page 44: Setting Up The Emif Calibration Fpga Ip

    6. I/O PLL Reconfiguration 847921 | 2025.04.07 closest address that can be assigned for PLL2 is d’40, and for PLL3 is d’60. Quartus Prime reads the base address and knows which PLL on the chip to reconfigure. Note: I/O bank cannot simultaneously support a PLL running dynamic reconfiguration and an EMIF.

  • Page 45: Setting Up The Iopll Fpga Ip

    6. I/O PLL Reconfiguration 847921 | 2025.04.07 . If configuration parameters are set to the illegal configuration settings, I/O [8:0] PLL may lose the lock, which can lead to device reliability problems. Altera recommends that you strictly follow the guidelines as follows: •...

  • Page 46: Clearing Off Calibration Statuses

    6. I/O PLL Reconfiguration 847921 | 2025.04.07 Address Bus Value for HSIO I/O PLL Address Bus Value for HVIO I/O PLL Value Reconfiguration Reconfiguration 0x10 s0_axi4lite_awaddr [7:0] core_avl_address[8:0] I/O PLL Base Address s0_axi4lite_awaddr [20:13] 3’b101 s0_axi4lite_awaddr [23:21] 2. Set the LSB of data bus value to 1’b1 to enable read and write operation. 6.4.2.

  • Page 47: Recalibration Of I/O Pll

    6. I/O PLL Reconfiguration 847921 | 2025.04.07 6.4.4. Recalibration of I/O PLL 1. Set the address bus value according to the table below: Address Bus Value for HSIO I/O PLL Reconfiguration Value 0x88 s0_axi4lite_awaddr [7:0] I/O PLL Base Address s0_axi4lite_awaddr [20:13] 3’b101 s0_axi4lite_awaddr [23:21] 2.

  • Page 48: Address Bus And Data Bus Settings

    6. I/O PLL Reconfiguration 847921 | 2025.04.07 Port Name Direction Description s0_axi4lite_araddr input Read Address s0_axi4lite_arvalid input Read Address Valid s0_axi4lite_arready output Read Address Ready s0_axi4lite_rdata output Read Data s0_axi4lite_rresp output Read Response s0_axi4lite_rvalid output Read Valid s0_axi4lite_rready input Read Ready s0_axi4lite_awprot input Write Protection Type...
  • Page 49 6. I/O PLL Reconfiguration 847921 | 2025.04.07 Divide Settings Write Address Parameter Write Data Bus Description Bus Setting Setting (18) Odd Division • =Odd division data[17] Data[17] — = 0, odd division is disabled. Data[17] The selected counter duty cycle = high_count total_count •...
  • Page 50 6. I/O PLL Reconfiguration 847921 | 2025.04.07 Divide Settings Write Address Parameter Write Data Bus Description Bus Setting Setting 0x64 High Count • data[7:0] Data[7:0] high_count • Data[30:23] low_count Low Count data[30:23] — total_count high_count low_count (18) Odd Division • =Odd division data[31] Data[31]...
  • Page 51 6. I/O PLL Reconfiguration 847921 | 2025.04.07 Divide Settings Write Address Parameter Write Data Bus Description Bus Setting Setting Bypass • =bypass enable data[8] Data[8] (18) Enable — =1, bypass is enabled. The Data[8] counter is bypassed with counter division value = 1. Phase Shift •...

  • Page 52: Data Bus Setting For Clock Gating Reconfiguration

    6. I/O PLL Reconfiguration 847921 | 2025.04.07 Divide Settings Write Address Parameter Write Data Bus Description Bus Setting Setting Charge Pump 0x44 Charge Pump • = Charge Pump Setting data[15:1] Data[15:1] Current Settings — Configure charge pump setting [15:1] — For more information about the Reconfiguration table, refer to the Address Bus and Data Bus Settings.
  • Page 53 6. I/O PLL Reconfiguration 847921 | 2025.04.07 Multiply Factor Charge Pump Settings Charge Pump Settings Charge Pump Settings [15:11] [10:6] [5:1] 00001 01001 01110 00001 01001 01110 00000 01000 01100 00000 00110 01001 00000 00110 00110 00000 00101 00101 00000 00011 00011 00000...

  • Page 54: Document Revision History For The Clocking And Pll User Guide: Agilex 3 Fpgas And Socs

    Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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