Indexed By Offset Nn; Address Register Indirect — Postdecrement - Motorola DSP56000 Manual

24-bit digital signal processor
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EXAMPLE: MOVE Y0,Y: (R3)-
BEFORE EXECUTION
Y1
47
1 2
3
1
2
23
$4735
$4734
Assembler Syntax: (Rn)–
Memory Spaces: P:, X:, Y:, XY:, L:
Additional Instruction Execution Time (Clocks): 0
Additional Effective Address Words: 0
Figure 4-6 Address Register Indirect — Postdecrement
ify the contents of Rn without an associated data move.
4.4.1.6

Indexed By Offset Nn

The address of the operand is the sum of the contents of the address register, Rn, and
the contents of the address offset register, Nn (see Table 4-1 and Figure 4-9). The con-
tents of the Rn and Nn registers are unchanged. This addressing mode, which requires
4 - 12
ADDRESSING
Y0
24 23
0
3
4 5
6
4
5
6
0 23
0
Y MEMORY
23
0
X X X X X X
X X X X X X
15
0
R3
$4735
15
0
N3
XXXX
15
0
M3
$FFFF
ADDRESS GENERATION UNIT
AFTER EXECUTION
Y1
47
24 23
1 2
3
1
2
3
4
5
23
0 23
Y MEMORY
23
$4735
4 5
6
X X X X X X
$4734
15
R3
15
N3
15
M3
Y0
0
6
4
5
6
0
0
4
5
6
0
$4734
0
XXXX
0
$FFFF
MOTOROLA

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