Motorola DSP56000 Manual page 21

24-bit digital signal processor
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The DSP56K family is not designed for a particular application but is designed to execute
commonly used DSP benchmarks in a minimum time for a single-multiplier architecture.
For example, a cascaded, 2nd-order, four-coefficient infinite impulse response (IIR) bi-
quad section has four multiplies for each section. For that algorithm, the theoretical
minimum number of operations for a single-multiplier architecture is four per section. Ta-
ble 1-1 shows a list of benchmarks with the number of instruction cycles a DSP56K chip
uses compared to the number of multiplies the algorithm requires.
Table 1-1 Benchmark Summary in Instruction Cycles
Benchmark
Real Multiply
N Real Multiplies
Real Update
N Real Updates
N Term Real Convolution (FIR)
N Term Real * Complex Convolution
Complex Multiply
N Complex Multiplies
Complex Update
N Complex Updates
N Term Complex Convolution (FIR)
th
N
- Order Power Series
nd
2
- Order Real Biquad Filter
nd
N Cascaded 2
N Radix Two FFT Butterflies
These benchmarks and others are used independently or in combination to implement
functions whose characteristics are controlled by the coefficients of the benchmarks being
executed. Useful functions using these and other benchmarks include the following:
1- 6
ORIGIN OF DIGITAL SIGNAL PROCESSING
- Order Biquads
DSP56K FAMILY INTRODUCTION
Number of Cycles
3
2N
4
2N
N
2N
6
4N
7
4N
4N
2N
7
4N
6N
Number of
Algorithm
Multiplies
1
N
1
N
N
N
4
N
4
4N
4N
2N
4
4N
4N
MOTOROLA

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