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DSP56000
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Motorola DSP56000 Manual Page 337
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Page
337
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6 - Table Of Contents
Page 7 - Table Of Contents
Page 8 - Table Of Contents
Page 9 - Table Of Contents
Page 10 - Table Of Contents
Page 11 - Table Of Contents
Page 12 - Table Of Contents
Page 13 - Table Of Contents
Page 14
Page 15
Page 16
Page 17 - INTRODUCTION
Page 18 - Analog Signal Processing
Page 19 - Digital Signal Processing
Page 20
Page 21
Page 22
Page 23
Page 24 - SUMMARY OF DSP56K FAMILY FEATURES
Page 25
Page 26 - MANUAL ORGANIZATION
Page 27
Page 28 - DSP56K CENTRAL ARCHITECTURE OVERVIEW
Page 29 - DATA BUSES
Page 30 - DATA ALU
Page 31
Page 32
Page 33 - MEMORY EXPANSION PORT (PORT A)
Page 34
Page 35
Page 36 - DATA ARITHMETIC LOGIC UNIT
Page 37 - DSP56K Block Diagram
Page 38 -
Page 39
Page 40 - MAC Unit
Page 41 - DATA ALU Accumulator Registers
Page 42
Page 43 - DATA REPRESENTATION AND ROUNDING
Page 44 - Integer-to-Fractional Data Conversion
Page 45 - Bit Weighting and Alignment of Operands
Page 46 - Integer/Fractional Number Comparison
Page 47 - Integer/Fractional Multiplication Compar...
Page 48 - Convergent Rounding
Page 49 - DOUBLE PRECISION MULTIPLY MODE
Page 50
Page 51
Page 52 - DATA ALU PROGRAMMING MODEL
Page 53
Page 54
Page 55
Page 56 - ADDRESS GENERATION UNIT AND ADDRESSING M...
Page 57 -
Page 58 - AGU Block Diagram
Page 59 - PROGRAMMING MODEL
Page 60 - AGU Programming Model
Page 61 - ADDRESSING
Page 62
Page 63 - Address Register Indirect — No Update
Page 64 - Address Register Indirect — Postincrem...
Page 65 - Address Register Indirect — Postdecrem...
Page 66 - Address Register Indirect — Postincrem...
Page 67 - Address Register Indirect — Postdecrem...
Page 68 - Address Register Indirect — Indexed by...
Page 69 - Address Register Indirect — Predecreme...
Page 70
Page 71 - Address Modifier Summary
Page 72 - Circular Buffer
Page 73 - Linear Addressing with a Modulo Modifier
Page 74 - Modulo Modifier Example
Page 75
Page 76 - Bit-Reverse Addressing Sequence Example
Page 77 - Bit-Reverse Address Calculation Example
Page 78
Page 79 -
Page 80
Page 81
Page 82 - PROGRAM CONTROL UNIT
Page 83 -
Page 84 - PROGRAM CONTROL UNIT (PCU) ARCHITECTURE
Page 85
Page 86 - Three-Stage Pipeline
Page 87 - Program Control Unit Programming Model
Page 88 - Status Register Format
Page 89
Page 90
Page 91
Page 92
Page 93 - OMR Format
Page 94 - Stack Pointer Register Format
Page 95 - SP Register Values
Page 96
Page 97 - DSP56K Central Processing Module Program...
Page 98
Page 99
Page 100 - INSTRUCTION SET INTRODUCTION
Page 101 -
Page 102 - General Format of an Instruction Operati...
Page 103 - Operand Sizes
Page 104 - Reading and Writing the ALU Extension Re...
Page 105 - Reading and Writing Control Registers
Page 106
Page 107
Page 108
Page 109
Page 110
Page 111
Page 112
Page 113 - Special Addressing – Immediate Data
Page 114 - Special Addressing – Absolute Addressi...
Page 115
Page 116 - Special Addressing – Short Jump Addres...
Page 117 - INSTRUCTION GROUPS
Page 118 - Special Addressing – I/O Short Address
Page 119
Page 120
Page 121
Page 122 - Hardware DO Loop
Page 123
Page 124 - Nested DO Loops
Page 125 - Parallel Move Examples
Page 126
Page 127
Page 128 - processing states
Page 129
Page 130 - PROCESSING STATES
Page 131
Page 132
Page 133
Page 134
Page 135
Page 136
Page 137 - EXCEPTION PROCESSING STATE (INTERRUPT PR...
Page 138
Page 139
Page 140 - Fast and Long Interrupt Examples
Page 141 - Interrupt Priority Register (Addr X:$FFF...
Page 142 - Interrupt Priority Level Bits
Page 143 - Interrupt Sources
Page 144 - Interrupting an SWI
Page 145
Page 146 - Illegal Instruction Interrupt Serviced b...
Page 147 - Illegal Instruction Interrupt Serviced b...
Page 148 - Repeated Illegal Instruction
Page 149
Page 150 - Trace Exception
Page 151
Page 152
Page 153
Page 154 - Fast Interrupt Service Routine
Page 155 - Two Consecutive Fast Interrupts
Page 156
Page 157 - Long Interrupt Service Routine
Page 158 - JSR First Instruction of a Fast Interrup...
Page 159 - JSR Second Instruction of a Fast Interru...
Page 160 - RESET PROCESSING STATE
Page 161 - Interrupting an REP Instruction
Page 162 - Interrupting Sequential REP Instructions
Page 163 - WAIT PROCESSING STATE
Page 164 - STOP PROCESSING STATE
Page 165 - STOP Instruction Sequence
Page 166 - STOP Instruction Sequence Followed by IR...
Page 167
Page 168
Page 169 - STOP Instruction Sequence Recovering wit...
Page 170
Page 171
Page 172
Page 173 - PORT A OVERVIEW
Page 174 - Port A Signals
Page 175 - port a interface
Page 176
Page 177
Page 178
Page 179
Page 180
Page 181 - PLL CLOCK OSCILLATOR INTRODUCTION
Page 182
Page 183 - pll components
Page 184 - PLL Control Register (PCTL)
Page 185 - Division Factor Bits DF0-DF3
Page 186
Page 187 - PSTP and PEN Relationship
Page 188 - PLL PINS
Page 189
Page 190 - PLL OPERATION CONSIDERATIONS
Page 191
Page 192
Page 193
Page 194
Page 195
Page 196 - ON-CHIP EMULATION INTRODUCTION
Page 197 -
Page 198 - Chip Status Information
Page 199 - OnCE CONTROLLER AND SERIAL INTERFACE
Page 200 - OnCE Command Register
Page 201
Page 202 - OnCE Status and Control Register (OSCR)
Page 203 - Memory Breakpoint Control Table
Page 204 - OnCE MEMORY BREAKPOINT LOGIC
Page 205 -
Page 206 - OnCE TRACE LOGIC
Page 207 - OnCE Trace Logic Block Diagram
Page 208 - METHODS OF ENTERING THE DEBUG MODE
Page 209 - PIPELINE INFORMATION AND GLOBAL DATA BUS...
Page 210 - OnCE Pipeline Information and GDB Regist...
Page 211 - PROGRAM ADDRESS BUS HISTORY BUFFER
Page 212 - SERIAL PROTOCOL DESCRIPTION
Page 213 - DSP56K TARGET SITE DEBUG SYSTEM REQUIREM...
Page 214
Page 215
Page 216
Page 217
Page 218
Page 219
Page 220
Page 221
Page 222
Page 223
Page 224 - USER SUPPORT
Page 225 - MOTOROLA DSP PRODUCT SUPPORT
Page 226
Page 227 - DSP56KADSx APPLICATION DEVELOPMENT SYSTE...
Page 228 - Dr. BuB ELECTRONIC BULLETIN BOARD
Page 229
Page 230
Page 231
Page 232
Page 233
Page 234
Page 235
Page 236
Page 237 - MOTOROLA DSP NEWS
Page 238 - TRAINING COURSES – (602) 897-3665 or (...
Page 239
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Page 270
Page 271 - A.1 APPENDIX A INTRODUCTION
Page 272
Page 273 - A.3 NOTATION
Page 274
Page 275
Page 276
Page 277
Page 278
Page 279 - A.4 ADDRESSING MODES
Page 280
Page 281
Page 282
Page 283
Page 284 - A.5 CONDITION CODE COMPUTATION
Page 285
Page 286
Page 287
Page 288
Page 289 - A.6 PARALLEL MOVE DESCRIPTIONS
Page 290 - A.7 INSTRUCTION DESCRIPTIONS
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Page 565 - B.1 INTRODUCTION
Page 566 - B-1 27-MHz Benchmark Results for the DSP...
Page 567
Page 568 - B-1 20-Tap FIR Filter Example
Page 569
Page 570
Page 571
Page 572 - B-2 Radix 2, In-Place, Decimation-In-Tim...
Page 573
Page 574 - B-5 Real Input FFT Based on Glenn Bergla...
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Contents
Table of Contents
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BTST
Instruction Format:
BTST
#n,X:pp
BTST
#n,Y:pp
Opcode:
23
0
0
0
0
Instruction Fields:
#n=bit number=bbbbb,
ea=6-bit I/O Short Address=pppppp
I/O Short Address pppppp
000000
•
•
111111
Timing: 4+mvb oscillator clock cycles
Memory: 1+ea program words
A - 68
INSTRUCTION DESCRIPTIONS
Bit Test
16 15
1
0
1
1
1
0
p
INSTRUCTION SET DETAILS
8
7
p
p
p
p
p
0
Memory SpaceS
X Memory
0
Y Memory
1
BTST
0
S
1
b
b
b
b
b
Bit Number bbbbb
00000
•
10111
MOTOROLA
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