INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i
= INTERRUPT
ii
= INTERRUPT INSTRUCTION WORD
n = NORMAL INSTRUCTION WORD
Figure 7-16 Simultaneous Wait Instruction and Interrupt
7.6
STOP PROCESSING STATE
The STOP instruction brings the processor into the stop processing state, which is the
lowest power consumption state. In the stop state, the clock oscillator is gated off;
whereas, in the wait state, the clock oscillator remains active. The chip clears all periph-
eral interrupts and external interrupts (IRQA, IRQB, and NMI) when it enters the stop
state. Trace or stack errors that were pending, remain pending. The priority levels of the
peripherals remain as they were before the STOP instruction was executed. The on-chip
peripherals are held in their respective individual reset states while in the stop state.
MOTOROLA
STOP PROCESSING STATE
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
n3
n4
—
—
n2
WAIT
—
—
n1
n2
WAIT
—
1
2
3
4
PROCESSING STATES
i
i
—
—
—
—
—
—
—
—
—
—
—
—
5
6
7
8
EQUIVALENT TO EIGHT NOPs
ii1
ii2
n4
—
ii1
ii2
—
—
ii1
9
10
11
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