PERIPHERAL
MODULES
24-Bit
56K Mod-
INTERNAL
DATA
BUS
SWITCH
PLL
PROGRAM
INTERRUPT
CLOCK
CONTROLLER
GENERATOR
9.2.1
Phase Detector and Charge Pump Loop Filter
The Phase Detector (PD) detects any phase difference between the external clock
(EXTAL) and an internal clock phase from the frequency multiplier. At the point where
there is negligible phase difference and the frequency of the two inputs is identical, the
PLL is in the "locked" state.
9 - 4
PLL COMPONENTS
PROGRAM
RAM/ROM
EXPANSION
YAB
ADDRESS
XAB
GENERATION
PAB
UNIT
YDB
XDB
PDB
GDB
PROGRAM
PROGRAM
DECODE
ADDRESS
GENERA TOR
CONTROLLER
Program Control Unit
MODC/NMI
MODB/IRQB
MODA/IRQA
RESET
Figure 9-2 DSP56K Block Diagram
PLL CLOCK OSCILLATOR
X MEMORY
Y MEMORY
RAM/ROM
RAM/ROM
EXPANSION
EXPANSION
DATA ALU
24X24 + 56 → 56-BIT MAC
TWO 56-BIT ACCUMULATORS
EXPANSION
AREA
EXTERNAL
ADDRESS
BUS
SWITCH
BUS
CONTROL
EXTERNAL
DATA BUS
SWITCH
OnCE™
16 BITS
24 BITS
MOTOROLA