Program Control Unit (Pcu) Architecture; Section 5.3 Program Control Unit (Pcu) Architecture; Program Decode Controller; Program Address Generator (Pag) - Motorola DSP56000 Manual

24-bit digital signal processor
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PROGRAM CONTROL UNIT (PCU) ARCHITECTURE

The program control unit implements a three-stage (prefetch, decode, execute) pipeline
and controls the five processing states of the DSP: normal, exception, reset, wait, and
stop.
5.3
PROGRAM CONTROL UNIT (PCU) ARCHITECTURE
The PCU consists of three hardware blocks: the program decode controller (PDC), the
program address generator (PAG), and the program interrupt controller (PIC).

5.3.1 Program Decode Controller

The PDC contains the program logic array decoders, the register address bus generator,
the loop state machine, the repeat state machine, the condition code generator, the inter-
rupt state machine, the instruction latch, and the backup instruction latch. The PDC
decodes the 24-bit instruction loaded into the instruction latch and generates all signals
necessary for pipeline control. The backup instruction latch stores a duplicate of the
prefetched instruction to optimize execution of the repeat (REP) and jump (JMP)
instructions.

5.3.2 Program Address Generator (PAG)

The PAG contains the PC, the SP, the SS, the operating mode register (OMR), the SR,
the LC register, and the LA register (see Figure 5-1).
The PAG provides hardware dedicated to support loops, which are frequent constructs in
DSP algorithms. A DO instruction loads the LC register with the number of times the loop
should be executed, loads the LA register with the address of the last instruction word in
the loop (fetched during one loop pass), and asserts the loop flag in the SR. The DO in-
struction also supports nested loops by stacking the contents of the LA, LC, and SR prior
to the execution of the instruction. Under control of the PAG, the address of the first in-
struction in the loop is also stacked so the loop can be repeated with no overhead. While
the loop flag in the SR is asserted, the loop state machine (in the PDC) will compare the
PC contents to the contents of the LA to determine if the last instruction word in the loop
was fetched. If the last word was fetched, the LC contents are tested for one. If LC is not
equal to one, then it is decremented, and the SS is read to update the PC with the address
of the first instruction in the loop, effectively executing an automatic branch. If the LC is
equal to one, then the LC, LA, and the loop flag in the SR are restored with the stack con-
tents, while instruction fetches continue at the incremented PC value (LA + 1). More
information about the LA and LC appears in Section 5.3.4 Instruction Pipeline Format.
The repeat (REP) instruction loads the LC with the number of times the next instruction is
to be repeated. The instruction to be repeated is only fetched once, so throughput is in-
creased by reducing external bus contention. However, REP instructions are not
MOTOROLA
PROGRAM CONTROL UNIT
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