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STOP PROCESSING STATE
the period of the first oscillator cycles will be irregular; thus, an additional period of
19,000 T cycles should be allowed for oscillator irregularity (the specification recom-
mends a total minimum period of 150,000 T cycles for oscillator stabilization). If an exter-
nal oscillator is used that is already stabilized, no additional time is needed.
The PLL may be disabled or not when the chip enters the STOP state. If it is disabled
and will not be re-enabled when the chip leaves the STOP state, the number of T cycles
will be much greater because the PLL must regain lock.
If the STOP instruction is executed when the IRQA signal is asserted, the clock genera-
tor will not be stopped, but the four-phase clock will be disabled for the duration of the
128K T cycle (or 16 T cycle) delay count. In this case, the STOP looks like a 131,072 T +
35 T cycle (or 51 T cycle) NOP, since the STOP instruction itself is eight instruction
cycles long (32 T) and synchronization of IRQA is 3T, which equals 35T.
A trace or stack error interrupt pending before entering the stop state is not cleared and
will remain pending. During the clock stabilization delay, all peripheral and external inter-
rupts are cleared and ignored (includes all SCI, SSI, HI, IRQA, IRQB, and NMI interrupts,
but not trace or stack error). If the SCI, SSI, or HI have interrupts enabled in 1) their
respective control registers and 2) in the interrupt priority register, then interrupts like SCI
transmitter empty will be immediately pending after the clock recovery delay and will be
serviced before continuing with the next instruction. If peripheral interrupts must be dis-
abled, the user should disable them with either the control registers or the interrupt prior-
ity register before the STOP instruction is executed.
If RESET is used to restart the processor (see Figure 7-19), the 128K T cycle delay
counter would not be used, all pending interrupts would be discarded, and the processor
would immediately enter the reset processing state as described in Section 7.4. For
example, the stabilization time recommended in theDSP56001 Technical Data Sheet for
the clock (RESET should be asserted for this time) is only 50 T for a stabilized external
clock but is the same 150,000 T for the internal oscillator. These stabilization times are
recommended and are not imposed by internal timers or time delays. The DSP fetches
instructions immediately after exiting reset. If the user wishes to use the 128K T (or 16 T)
delay counter, it can be started by asserting IRQA for a short time (about two clock
cycles).
MOTOROLA
PROCESSING STATES
7 - 41

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