Motorola DSP56000 Manual page 511

24-bit digital signal processor
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NOT
Operation:
D[47:24]
D[47:24] (parallel move)
where "—" denotes the logical NOT operator
Description: Take the ones complement of bits 47–24 of the destination operand D and
store the result back in bits 47–24 of the destination accumulator. This is a 24-bit opera-
tion. The remaining bits of D are not affected.
Example:
NOT A1 AB,L:(R2)+
Before Execution
A
$00:123456:789ABC
Explanation of Example: Prior to execution, the 56-bit A accumulator contains the
value $00:123456:789ABC. The NOT A instruction takes the ones complement of bits
47–24 of the A accumulator (A1) and stores the result back in the A1 register. The
remaining bits of the A accumulator are not affected.
Condition Codes:
5
14
13
1
LF
DM
S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION
L — Set if data limiting has occurred during parallel move
N — Set if bit 47 of A or B result is set
Z — Set if bits 47-24 of A or B result are zero
V — Always cleared
A - 242
INSTRUCTION DESCRIPTIONS
Logical Complement
;save A1,B1, take the ones complement of A1
12
11
10
9
T
**
S1
S0
I1
MR
INSTRUCTION SET DETAILS
Assembler Syntax:
NOT
After Execution
A
$00:EDCBA9:789AB
8
7
6
5
4
I0
S
L
E
U
CCR
NOT
D (parallel move)
3
2
1
0
N
Z
V
C
MOTOROLA

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