EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
7.3.6 Instructions Preceding the Interrupt Instruction Fetch
The following one-word instructions are aborted when they are fetched in the cycle pre-
ceding the fetch of the first interrupt instruction word — REP, STOP, WAIT, RESET, RTI,
RTS, Jcc, JMP, JScc, and JSR.
Two-word instructions are aborted when the first interrupt instruction word fetched will
replace the fetch of the second word of the two-word instruction. Aborted instructions are
refetched when program control returns from the interrupt routine. The PC is adjusted
appropriately before the end of the decode cycle of the aborted instruction.
If the first interrupt word fetch occurs in the cycle following the fetch of a one-word
instruction not previously listed or the second word of a two-word instruction, that instruc-
tion will complete normally before the start of the interrupt routine.
The following cases have been identified where service of an interrupt might encounter
an extra delay:
1. If a long interrupt routine is used to service an SWI, then the processor priority
level is set to 3. Thus, all interrupts except other level-3 interrupts are disabled
until the SWI service routine terminates with an RTI (unless the SWI service
routine software lowers the processor priority level).
2. While servicing an interrupt, the next interrupt service will be delayed accord-
ing to the following rule: after the first interrupt instruction word reaches the
instruction decoder, at least three more instructions will be decoded before
decoding the next first interrupt instruction word. If any one pair of instructions
being counted is the REP instruction followed by an instruction to be repeated,
then the combination is counted as two instructions independent of the num-
ber of repeats done. Sequential REP combinations will cause pending inter-
rupts to be rejected and can not be interrupted until the sequence of REP
3. The following instructions are not interruptible: SWI, STOP, WAIT, and
4. The REP instruction and the instruction being repeated are not interruptible.
5. If the trace bit in the SR (DSP56000/56001 only) is set, the only interrupts that
will be processed are the hardware RESET, III,NMI, stack error, and trace.
Peripheral and external interrupt requests will be ignored. The interrupt gener-
ated by the SWI instruction will be ignored.
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