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Motorola DSP56000 Manual: Once Memory Breakpoint Logic

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10.3.4.4
Software Debug Occurrence (SWO) Bit 8
This read-only status bit is set when the processor enters debug mode of operation as a
result of the execution of the DEBUG or DEBUGcc instruction with condition true. This bit
is cleared on hardware reset or when leaving the debug mode with the GO and EX bits
set.
10.3.4.5
Memory Breakpoint Occurrence (MBO) Bit 9
This read-only status bit is set when a memory breakpoint occurs. This bit is cleared on
hardware reset or when leaving the debug mode with the GO and EX bits set.
10.3.4.6
Trace Occurrence (TO) Bit 10
This read-only status bit is set when the processor enters debug mode of operation, when
the trace counter is zero and the trace mode has been armed. This bit is cleared on hard-
ware reset or when leaving the debug mode with the GO and EX bits set.
10.4

OnCE MEMORY BREAKPOINT LOGIC

Memory breakpoints may be set on program memory or data memory locations. Also, the
breakpoint does not have to be in a specific memory address but within an address range
of where the program may be executing. This significantly increases the programmer's
ability to monitor what the program is doing in real-time.
The breakpoint logic contains a latch for the addresses, registers that store the upper and
lower address limit, comparators, and a breakpoint counter. Figure 10-6 illustrates the
block diagram of the OnCE Memory Breakpoint Logic.
Address comparators help to determine where a program may be getting lost or when
data is being written to areas that should not be written to. They are also useful in halting
a program at a specific point to examine/change registers or memory. Using address com-
parators to set breakpoints enables the user to set breakpoints in RAM or ROM in any op-
erating mode. Memory accesses are monitored according to the contents of the OSCR.
The low address comparator will generate a logic true signal when the address on the bus
is greater than or equal to the contents of the lower limit register. The high address com-
parator will generate a logic true signal when the address on the bus is less than or equal
to the contents of the upper limit register. If the low address comparator and high address
comparator both issue a logic true signal, the address is within the address range and the
breakpoint counter is decremented if the contents are greater than zero. If zero, the
counter is not decremented and the breakpoint exception occurs (ISBKPT asserted).
10.4.1 Memory Address Latch (OMAL)
The Memory Address Latch is a 16-bit register that latches the PAB, XAB or YAB on every
instruction cycle according to the BC3-BC0 bits in OSCR.
10- 12
OnCE MEMORY BREAKPOINT LOGIC
ON-CHIP EMULATION (OnCE)
MOTOROLA

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