Motorola DSP56000 Manual page 474

24-bit digital signal processor
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X: Y:
Register w
S1, D1 e e
Read S1 0
X0
Write D1 1
X1
A
B
where "tt" refers to an address register R4 - R7 or R0 - R3 which is in the opposite
address register bank from the one used in the X effective address, previously described
Register W
S2, D2 f f
Read S2 0
Y0
Write D2 1
Y1
A
B
Timing: mv oscillator clock cycles
Memory: mv program words
MOTOROLA
INSTRUCTION DESCRIPTIONS
XY Memory Data Move
S1
D1
S/L Sign Ext Zero
0 0
no
no
0 1
no
no
1 0 yes
A2
1 1 yes
B2
S2
D2
S/L Sign Ext Zero
0 0
no
no
0 1
no
no
1 0 yes
A2
1 1 yes
B2
INSTRUCTION SET DETAILS
D1
Y Effective
Addressing Mode
no
(Rn) +Nn
no
(Rn) -
A0
(Rn) +
B0
(Rn)
D2
no
no
A0
B0
X: Y:
m m r r
0 1 t t
1 0 t t
1 1 t t
0 0 t t
A - 205

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