EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i
= INTERRUPT
ii
= INTERRUPT INSTRUCTION WORD
II = ILLEGAL INSTRUCTION
n = NORMAL INSTRUCTION WORD
Figure 7-5 Illegal Instruction Interrupt Serviced by a Long Interrupt
7 - 20
MAIN
PROGRAM
FETCHES
II (NOP)
n6
NO FETCH
NO FETCH
(a) Instruction Fetches from Memory
ILLEGAL INSTRUCTION INTERRUPT
n1
n2
n3
n4
n1
n2
n3
n1
n2
1
2
3
4
5
(b) Program Controller Pipeline
PROCESSING STATES
LONG INTERRUPT
SERVICE ROUTINE
FETCHES
RECOGNIZED AS PENDING
ILLEGAL INSTRUCTION INTERRUPT
RECOGNIZED AS PENDING
i
i
n5
n6
—
—
ii1
n4
II
—
—
—
n3
n4
NOP
—
—
6
7
8
9
10
I1
I2
I3
I4
I5
ii2
ii3
ii4
ii5
ii1
ii2
ii3
ii4
—
ii1
ii2
ii3
11
12
13
14
MOTOROLA