Predecrement By 1; Address Register Indirect — Postincrement By Offset Nn - Motorola DSP56000 Manual

24-bit digital signal processor
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EXAMPLE: MOVE X1,X: (R2)+N2
BEFORE EXECUTION
X1
47
24 23
A
5
B 4
C
6
23
0 23
$3204
$3200
Assembler Syntax: (Rn)+Nn
Memory Spaces: P:, X:, Y:, XY:, L:
Additional Instruction Execution Time (Clocks): 0
Additional Effective Address Words: 0
Figure 4-7 Address Register Indirect — Postincrement by Offset Nn
an extra instruction cycle, cannot be used for making XY: memory references.
4.4.1.7

Predecrement By 1

The address of the operand is the contents of the address register, Rn, decremented by
1 before the operand address is used (see Table 4-1 and Figure 4-10). The contents of
Rn are decremented and stored in the same address register. This addressing mode re-
quires an extra instruction cycle. This mode cannot be used for making XY: memory
references, nor can it be used for modifying the contents of Rn without an associated data
MOTOROLA
ADDRESSING
X0
0
0 0
0
0
0
1
0
X MEMORY
23
0
X X X X X X
X X X X X X
15
0
R2
$3200
15
0
$0004
N2
15
0
M2
$FFFF
ADDRESS GENERATION UNIT
AFTER EXECUTION
X1
47
24 23
A
5
B
4
C
6
0
0
23
0 23
X MEMORY
23
$3204
X X X X X X
$ A 5 B 4 C 6
$3200
15
R2
15
N2
15
M2
X0
0
0
0
0
1
0
0
0
$3204
0
$0004
0
$FFFF
4 - 13

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