be subdivided into three additional groups: read/write control (RD and WR), address
space selection (including program memory select (PS), data memory select (DS), and X/
Y select) and bus access control.
The read/write controls are self-descriptive. They can be used as decoded read and write
controls, or, the write signal can be used as the read/write control and the read signal can
be used as an output enable (or data enable) control for the memory. Decoding in this
fashion simplifies the connection to high-speed random-access memories (RAMs). The
address space selection signals can be considered as additional address signals, which
extend the addressable memory from 64K words to 192K words
Note: Depending on system design, unused inputs should have pullup resistors for two
reasons: 1) floating inputs draw excessive power, and 2) a floating input can cause erro-
neous operation. For example, during RESET, all signals are three-stated. Output pins PS
and DS may require pullup resistors because, without them, the signals may become ac-
tive and may cause two or more memory chips to try to simultaneously drive the external
data bus, which can damage the memory chips. A pullup resistor in the 50K-ohm range
should be sufficient.
8.2.1 Read/Write Control Signals
The following paragraphs describe the Port A read/write control signals. These pins are
three-stated during reset and may require pullup resistors to prevent erroneous operation
of a memory device or other external components.
Program Memory Select (PS)
This three-state output is asserted only when external program memory is referenced.
Data Memory Select (DS)
This three-state output is asserted only when external data memory is referenced.
X/Y Select (X/Y)
This three-state output selects which external data memory space (X or Y) is referenced
8.2.2 Port A Address and Data Bus Signals
The following paragraphs describe the Port A address and data bus signals. These pins
are three-stated during reset and may require pullup resistors to prevent erroneous
PORT A INTERFACE
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