Motorola DSP56000 Manual page 398

24-bit digital signal processor
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JSCLR
Notes: If A or B is specified as the destination operand, the following sequence of events
takes place:
1. The S bit is computed according to its definition (See Section A.5)
2. The accumulator value is scaled according to the scaling mode bits S0
and S1 in the status register (SR).
3. If the accumulator extension is in use, the output of the shifter is limited to
the maximum positive or negative saturation constant, and the L bit is set.
4. The bit test is performed on the resulting 24-bit value, and the jump to sub-
routine is taken if the bit tested is clear. The original contents of A or B are
not changed.
Timing: 6+jx oscillator clock cycles
Memory: 2 program words
MOTOROLA
INSTRUCTION DESCRIPTIONS
Jump to Subroutine if Bit Clear
INSTRUCTION SET DETAILS
JSCLR
A - 129

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