Division Factor Bits Df0-Df3 - Motorola DSP56000 Manual

11
MF11 MF10
23
** CKOS
Reserved bits, read as zero, should be written with zero for future compatibility.
**
shows how to program the MF0-MF11 bits. The VCO will oscillate at a frequency of
MF x F , where F
ext ext
chosen to ensure that the resulting VCO output frequency will lay in the range specified
in the device's Technical Data Sheet. Any time a new value is written into the MF0-MF11
bits, the PLL will lose the lock condition. After a time delay, the PLL will relock. The
MF0-MF11 bits are set to a pre-determined value during hardware reset; the value is
implementation dependent and may be found in each DSP56K family member's user
manual.
Table 9-1 Multiplication Factor Bits MF0-MF11
9.2.5.2 PCTL Division Factor Bits (DF0-DF3) - Bits 12-15
The Division Factor Bits DF0-DF3 define the divide factor (DF) of the low power divider.
These bits specify any power of two divide factor in the range from 2
9 - 6
PLL COMPONENTS
10 9 8 7 6
MF9 MF8 MF7 MF6
22 21 20 19 18
CSRC COD1 COD0 PEN
Figure 9-3 PLL Control Register (PCTL)
is the EXTAL clock frequency. The multiplication factor must be
MF11-MF0
$000
$001
$002
•
•
$FFE
$FFF
PLL CLOCK OSCILLATOR
5 4 3 2
MF5 MF4 MF3 MF2
17 16 15 14
PSTP XTLD DF3 DF2
Multiplication
Factor MF
1
2
3
•
•
4095
4096
1 0
MF1 MF0
13 12
DF1 DF0
0 15
to 2 . Table 9-2
MOTOROLA