SP+1 SP; PC SSH; SR SSL; 0xxx PC
SP+ SP; PC SSH; SR SSL; ea PC
Description: Jump to the subroutine whose location in program memory is given by the
instruction's effective address. The address of the instruction immediately following the
JSR instruction (PC) and the system status register (SR) is pushed onto the system
stack. Program execution then continues at the specified effective address in program
memory. All memory alterable addressing modes may be used for the effective address.
A fast short jump addressing mode may also be used. The 12-bit data is zero extended
to form the effective address.
Restrictions: A JSR instruction used within a DO loop cannot specify the loop
address (LA) as its target.
A JSR instruction used within a DO loop cannot begin at the address LA within that DO
A JSR instruction cannot be repeated using the REP instruction.
Explanation of Example: In this example, program execution is transferred to the sub-
routine at address P:(R5) in program memory, and the contents of the R5 address regis-
ter are then updated.
The condition codes are not affected by this instruction.
A - 136
Jump to Subroutine
;jump to subroutine at (R5), update R5
INSTRUCTION SET DETAILS