Motorola DSP56000 Manual page 312

24-bit digital signal processor
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BCHG
Instruction Format:
BCHG
#n,X:ea
BCHG #n,Y:ea
Opcode:
23
0
0
0
0
Instruction Fields:
#n=bit number=bbbbb,
ea=6-bit Effective Address=MMMRRR
Effective
Addressing Mode
(Rn)-Nn
(Rn)+Nn
(Rn)-
(Rn)+
(Rn)
(Rn+Nn)
-(Rn)
Absolute address
where "rrr" refers to an address register R0-R7
Timing: 4+mvb oscillator clock cycles
Memory: 1+ea program words
MOTOROLA
INSTRUCTION DESCRIPTIONS
Bit Test and Change
16
15
1
0
1
1
0
1
M
OPTIONAL EFFECTIVE ADDRESS EXTENSION
M M M R R R
0 0 0 r r r
0 0 1 r r r
0 1 0 r r r
0 1 1 r r r
1 0 0 r r r
1 0 1 r r r
1 1 1 r r r
1 1 0 0 0 0
INSTRUCTION SET DETAILS
8
7
M
M
R
R
R
0
S
Memory SpaceS
X Memory
0
Y Memory
1
BCHG
0
0
b
b
b
b
b
Bit Number bbbbb
00000
10111
A - 43

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