Bclr - Motorola DSP56000 Manual

24-bit digital signal processor
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BCLR

Operation:
D[n]
C;
0
D[n]
D[n]
C;
0
D[n]
D[n]
C;
0
D[n]
D[n]
C;
0
D[n]
D[n]
C;
0
D[n]
D[n]
C;
0
D[n]
D[n]
C;
0
D[n]
Description: Test the n
the destination location. The state of the n
code register. The bit to be tested is selected by an immediate bit number from 0–23.
This instruction performs a read-modify-write operation on the destination location using
two destination accesses before releasing the bus. This instruction provides a test-and-
clear capability which is useful for synchronizing multiple processors using a shared
memory. This instruction can use all memory alterable addressing modes.
Example:
:
BCLR
#$E,X:<<$FFE4
:
Before Execution
X:$FFE4
SR
A - 48
INSTRUCTION DESCRIPTIONS
Bit Test and Clear
th
bit of the destination operand D, clear it and store the result in
th
;test and clear bit 14 in I/O Port B Data Reg.
$FFFFFF
$0300
INSTRUCTION SET DETAILS
Assembler Syntax:
BCLR
#n,X:ea
BCLR
#n,X:aa
BCLR
#n,X:pp
BCLR
#n,Y:ea
BCLR
#n,Y:aa
BCLR
#n,Y:pp
BCLR
#n,D
bit is stored in the carry bit C of the condition
After Execution
X:$FFE4
$FFBFFF
SR
$0301
BCLR
MOTOROLA

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