Syntax; Section 6.1 Instruction Set Introduction; Section 6.2 Syntax - Motorola DSP56000 Manual

6.1 INSTRUCTION SET INTRODUCTION
The programming model shown in Figure 6-1 suggests that the DSP56K central pro-
cessing module architecture can be viewed as three functional units which operate in
parallel: data arithmetic logic unit (data ALU), address generation unit (AGU), and pro-
gram control unit (PCU). The instruction set keeps each of these units busy throughout
each instruction cycle, achieving maximal speed and maintaining minimal program size.
This section introduces the DSP56K instruction set and instruction format. The complete
range of instruction capabilities combined with the flexible addressing modes used in this
processor provide a very powerful assembly language for implementing digital signal pro-
cessing (DSP) algorithms. The instruction set has been designed to allow efficient coding
for DSP high-level language compilers such as the C compiler. Execution time is mini-
mized by the hardware looping capabilities, use of an instruction pipeline, and parallel
moves.
6.2

SYNTAX

The instruction syntax is organized into four columns: opcode, operands, and two parallel-
move fields. The assembly-language source code for a typical one-word instruction is
shown in the following illustration. Because of the multiple bus structure and the parallel-
ism of the DSP, up to three data transfers can be specified in the instruction word – one
on the X data bus (XDB), one on the Y data bus (YDB), and one within the data ALU.
These transfers are explicitly specified. A fourth data transfer is implied and occurs in the
program control unit (instruction word prefetch, program looping control, etc.). Each data
transfer involves a source and a destination.
Opcode Operands
MAC X0,Y0,A
The opcode column indicates the data ALU, AGU, or program control unit operation to be
performed and must always be included in the source code. The operands column spec-
ifies the operands to be used by the opcode. The XDB and YDB columns specify optional
data transfers over the XDB and/or YDB and the associated addressing modes. The
address space qualifiers (X:, Y:, and L:) indicate which address space is being referenced.
Parallel moves are allowed in 30 of the 62 instructions. Additional information is presented
in APPENDIX A - INSTRUCTION SET DETAILS.
6.3 INSTRUCTION FORMATS
The DSP56K instructions consist of one or two 24-bit words – an operation word and an
optional effective address extension word. The general format of the operation word is
MOTOROLA
INSTRUCTION SET INTRODUCTION
XDB
X:(R0)+,X0
INSTRUCTION SET INTRODUCTION
YDB
Y:(R4)+,Y0
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