Motorola DSP56000 Manual page 433

24-bit digital signal processor
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INSTRUCTION DESCRIPTIONS
I
I
Immediate Short Data Move
Operation:
Assembler Syntax:
( . . . . . ), #xx D
( . . . . . ) #xx,D
where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves.
Description: Move the 8-bit immediate data value (#xx) into the destination operand D.
If the destination register D is A0, A1, A2, B0, B1, B2, R0–R7, or N0–N7, the 8-bit imme-
diate short operand is interpreted as an unsigned integer and is stored in the specified
destination register. That is, the 8-bit data is stored in the eight LS bits of the destination
operand, and the remaining bits of the destination operand D are zeroed.
If the destination register D is X0, X1, Y0, Y1, A, or B, the 8-bit immediate short operand
is interpreted as a signed fraction and is stored in the specified destination register.
That is, the 8-bit data is stored in the eight MS bits of the destination operand, and the
remaining bits of the destination operand D are zeroed.
If the arithmetic or logical opcode-operand portion of the instruction specifies a given
destination accumulator, that same accumulator or portion of that accumulator may not
be specified as a destination D in the parallel data bus move operation. Thus, if the
opcode-operand portion of the instruction specifies the 56-bit A accumulator as its desti-
nation, the parallel data bus move portion of the instruction may not specify A0, A1, A2,
or A as its destination D. Similarly, if the opcode-operand portion of the instruction speci-
fies the 56-bit B accumulator as its destination, the parallel data bus move portion of the
instruction may not specify B0, B1, B2, or B as its destination D. That is, duplicate des-
tinations are NOT allowed within the same instruction.
Note: Due to instruction pipelining, if an AGU register (Mn, Nn, or Rn) is directly changed
with this instruction, the new contents may not be available for use until the second fol-
lowing instruction. See the restrictions discussed in A.9.6 - R, N, and M Register Restric-
tions on page A-310.
A - 164
INSTRUCTION SET DETAILS
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