Motorola DSP56000 Manual page 107

24-bit digital signal processor
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BA
Accumulators B and A (B1:A1, 48 Bits)
A10
Accumulator A (A1:A0, 48 Bits)
B10
Accumulator B (B1:B0, 48 Bits)
Address ALU
Rn
Address Registers R0–R7 (16 Bits)
Nn
Address Offset Registers N0–N7 (16 Bits)
Mn
Address Modifier Registers M0–M7 (16 Bits)
Program Control Unit
PC
Program Counter (16 Bits)
MR
Mode Register (8 Bits)
CCR
Condition Code Register (8 Bits)
SR
Status Register (MR:CCR, 16 Bits)
OMR
Operating Mode Register (8 Bits)
LA
Hardware Loop Address Register (16 Bits)
LC
Hardware Loop Counter (16 Bits)
SP
System Stack Pointer (6 Bits)
SS
System Stack RAM (15X32 Bits)
SSH
Upper 16 Bits of the Contents of the Current Top of Stack
SSL
Lower 16 Bits of the Contents of the Current Top of Stack
Addresses
ea
Effective Address
xxxx
Absolute Address (16 Bits)
xxx
Short Jump Address (12 Bits)
aa
Absolute Short Address (6 Bits Zero Extended)
pp
I/O Short Address (6 Bits Ones Extended)
< . . . >
Contents of the Specified Address
X:
X Memory Reference
Y:
Y Memory Reference
L:
Long Memory Reference – X Concatenated with Y
P:
Program Memory Reference
Miscellaneous
#xx
Immediate Short Data (8 Bits)
#xxx
Immediate Short Data (12 Bits)
#xxxxxx
Immediate Data (24 Bits)
#n
Immediate Short Data (5 Bits)
S,Sn
Source Operand Register
D,Dn
Destination Operand Register
6 - 10
INSTRUCTION FORMATS
INSTRUCTION SET INTRODUCTION
*
MOTOROLA

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