Interrupting An Swi - Motorola DSP56000 Manual

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
When either the IRQA or IRQB pin is disabled in the interrupt priority register, the inter-
rupt request coming in on the pin will be ignored, regardless of whether the input was
defined as level sensitive or edge sensitive. If the interrupt input is defined as edge sen-
sitive, its edge-detection latch will remain in the reset state for as long as the interrupt pin
is disabled. If the interrupt is defined as level-sensitive, its edge-detection latch will stay
in the reset state. If the level-sensitive interrupt is disabled while it is pending it will be
cancelled. However, if the interrupt has been fetched, it normally will not be cancelled.
The processor begins interrupt service by fetching the instruction word in the first vector
location. The interrupt is considered finished when the processor fetches the instruction
word in the second vector location.
In an edge-triggered interrupt, the internal latch is automatically cleared when the sec-
ond vector location is fetched. The fetch of the first vector location does not guarantee
that the second location will be fetched. Figure 7-3 illustrates the one case where the
second vector location is not fetched. The SWI instruction in the figure discards the fetch
of the first interrupt vector to ensure that the SWI vectors will be fetched. Instruction n4 is
decoded as an SWI while ii1 is being fetched. Execution of the SWI requires that ii1 be
discarded and the two SWI vectors (ii3 and ii4) be fetched instead.
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION BEING DECODED
i = INTERRUPT REQUEST
i* = INTERRUPT REQUEST GENERATED BY SWI
ii1 = FIRST VECTOR OF INTERRUPT i
ii3 = FIRST SWI VECTOR (ONE-WORD JSR)
ii4 = SECOND SWI VECTOR
n = NORMAL INSTRUCTION WORD
n4 = SWI
sw = INSTRUCTIONS PERTAINING TO THE SWI LONG INTERRUPT ROUTINE
MOTOROLA
i i*
i
n3 n4 n5 ii1
n2 n3 SWI —
n1 n2 n3 SWI
1
Figure 7-3 Interrupting an SWI
PROCESSING STATES
i*
ii3 ii4 sw1
— — JSR —
NOP NOP NOP JSR
sw2 sw3 sw4
sw1 sw2 sw3
— sw1 sw2
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