Address Register Indirect — Indexed By Offset Nn - Motorola DSP56000 Manual

24-bit digital signal processor
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EXAMPLE: MOVE Y1,X: (R6+N6)
BEFORE EXECUTION
Y1
47
6 2 1
0
0
23
$6004
$6000
Assembler Syntax: (Rn+Nn)
Memory Spaces: P:, X:, Y:, L:
Additional Instruction Execution Time (Clocks): 2
Additional Effective Address Words: 0
Figure 4-9 Address Register Indirect — Indexed by Offset Nn
The contents of the address modifier register, Mn, defines the type of arithmetic to be per-
formed for addressing mode calculations. For modulo arithmetic, the contents of Mn also
specifies the modulus, or the size of the memory buffer whose addresses will be refer-
enced. See Table 4-2 for a summary of the address modifiers implemented on the
MOTOROLA
ADDRESSING
Y0
24 23
0
9
B
A
4
C
2
2
0 23
0
X MEMORY
23
0
X X X X X X
X X X X X X
15
0
R6
$6000
+
15
0
$0004
N6
15
0
M6
$FFFF
ADDRESS GENERATION UNIT
AFTER EXECUTION
Y1
47
24 23
6 2
1 0
0
9
B
A
23
0 23
X MEMORY
23
$6004
$ 6 2 1 0 0 9
X X X X X X
$6000
15
R6
15
N6
15
M6
Y0
0
4
C 2
2
0
0
0
$6000
0
$0004
0
$FFFF
4 - 15

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