Stop Instruction Sequence - Motorola DSP56000 Manual

The stop processing state halts all activity in the processor until one of the following
actions occurs:
1. A low level is applied to the IRQA pin.
2. A low level is applied to the RESET pin.
3. A low level is applied to the DR pin
Either of these actions will activate the oscillator, and, after a clock stabilization delay,
clocks to the processor and peripherals will be re-enabled. The clock stabilization delay
period is determined by the stop delay (SD) bit in the OMR.
The stop sequence is composed of eight instruction cycles called stop cycles. They are
differentiated from normal instruction cycles because the fourth cycle is stretched for an
indeterminate period of time while the four-phase clock is turned off.
The STOP instruction is fetched in stop cycle 1 of Figure 7-17, decoded in stop cycle 2
(which is where it is first recognized as a stop command), and executed in stop cycle 3.
The next instruction (n4) is fetched during stop cycle 2 but is not decoded in stop cycle 3
because, by that time, the STOP instruction prevents the decode. The processor stops
the clock and enters the stop mode. The processor will stay in the stop mode until it is
restarted.
IRQA
FETCH
DECODE
EXECUTE
STOP CYCLE COUNT
IRQA = INTERRUPT REQUEST A SIGNAL
n = NORMAL INSTRUCTION WORD
STOP = INTERRUPT INSTRUCTION WORD
7 - 38
STOP PROCESSING STATE
n3 n4 —
n2 STOP —
n1 n2 STOP
1 2 3
CLOCK STOPPED
Figure 7-17 STOP Instruction Sequence
PROCESSING STATES
—
—
—
4 5 6
RESUME STOP CYCLE COUNT 4,
INTERRUPTS ENABLED
131,072 T OR 16 T CYCLE COUNT STARTED
n4
7 8 (9)
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