Fast Interrupt Service Routine - Motorola DSP56000 Manual

24-bit digital signal processor
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EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
INTERRUPT SYNCHRONIZED
AND RECOGNIZED
AS PENDING
ADDITIONAL INTERRUPTS
DISABLED DURING
FAST INTERRUPT
INTERRUPTS
RE-ENABLED
ii = INTERRUPT INSTRUCTION
n = NORMAL INSTRUCTION
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i
= INTERRUPT
ii
= INTERRUPT INSTRUCTION WORD
n = NORMAL INSTRUCTION WORD
MOTOROLA
MAIN
PROGRAM
MEMORY
n1
n2
n3
n4
(a) Instruction Fetches from Memory
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
i
i
n1
n2
n1
1
2
(b) Program Controller Pipeline
Figure 7-8 Fast Interrupt Service Routine
PROCESSING STATES
ii1
ii2
n3
n4
n2
ii1
ii2
n3
n1
n2
ii1
ii2
3
4
5
6
ii1
ii2
INTERRUPTS RE-ENABLED
n4
n3
n4
7
8
7 - 27

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