Once Trace Logic; Section 10.5 Once Trace Logic - Motorola DSP56000 Manual

OnCE TRACE LOGIC

points, OMLLR must be loaded by the external command controller.
10.4.4 Memory High Address Comparator (OMHC)
The OMHC compares the current memory address (stored in OMAL) with the OMULR
contents. If OMULR is higher than or equal to OMAL then the comparator delivers a signal
indicating that the address is lower than or equal to the upper limit.
10.4.5 Memory Low Address Comparator (OMLC)
The OMLC compares the current memory address (stored in OMAL) with the OMLLR con-
tents. If OMLLR is lower than or equal to OMAL then the comparator delivers a signal in-
dicating that the address is higher than or equal to the lower limit.
10.4.6 Memory Breakpoint Counter (OMBC)
The 24-bit OMBC is loaded with a value equal to the number of times, minus one, that a
memory access event should occur before a memory breakpoint is declared. The memory
access event is specified by the BC3-BC0 bits in the OSCR register and by the memory
upper and lower limit registers. On each occurrence of the memory access event, the
breakpoint counter is decremented. When the counter has reached the value of zero and
a new occurrence takes place, the chip will enter the debug mode. The OMBC can be
read, written, or cleared through the OnCE serial interface.
Anytime the upper or lower limit registers are changed, or a different breakpoint event is
selected in the OSCR, the breakpoint counter must be written afterward. This assures that
the OnCE breakpoint logic is reset and that no previous events will affect the new break-
point event selected.
The breakpoint counter is cleared by hardware reset.
10.5 OnCE TRACE LOGIC
The OnCE trace logic allows the user to execute instructions in single or multiple steps
before the chip returns to the debug mode and awaits OnCE commands from the debug
serial port. (The OnCE trace logic is independent of the trace facility of the
DSP56000/56001, which is operated through the trace interrupt discussed in Section
7.3.3.3, and started by setting the trace bit in the processor's status register discussed in
Section 5.4.2.12). The OnCE trace logic block diagram is shown in Figure 10-7.
10- 14 ON-CHIP EMULATION (OnCE) MOTOROLA