DSP56001 Compatibility — All members of the DSP56K family are downward
compatible with the DSP56001, and also have added flexibility, speed, and
Low Power — As a CMOS part, the DSP56000/DSP56001 is inherently very low
power and the STOP and WAIT instructions further reduce power requirements.
This manual describes the central processing module of the DSP56K family in detail and
provides practical information to help the user:
Understand the operation of the DSP56K family
Design parallel communication links
Design serial communication links
Code DSP algorithms
Code communication routines
Code data manipulation algorithms
Locate additional support
The following list describes the contents of each section and each appendix:
Section 2 – DSP56K Central Architecture Overview
The DSP56K central architecture consists of the data arithmetic logic unit (ALU), ad-
dress generation unit (AGU), program control unit, On-Chip Emulation (OnCE)
circuitry, the phase locked loop (PLL) based clock oscillator, and an external memory
port (Port A). This section describes each subsystem and the buses interconnecting
the major components in the DSP56K central processing module.
Section 3 – Data Arithmetic Logic Unit
This section describes in detail the data ALU and its programming model.
Section 4 – Address Generation Unit
This section specifically describes the AGU, its programming model, address indirect
modes, and address modifiers.
Section 5 – Program Control Unit
This section describes in detail the program control unit and its programming model.
Section 6 – Instruction Set Introduction
This section presents a brief description of the syntax, instruction formats, oper-
and/memory references, data organization, addressing modes, and instruction set. A
detailed description of each instruction is given in APPENDIX A - INSTRUCTION SET
DSP56K FAMILY INTRODUCTION
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