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PROGRAM ADDRESS BUS HISTORY BUFFER
10.7.2 Pipeline Instruction Latch Register (OPILR)
The OPILR is a 24-bit latch that stores the value of the instruction latch before the debug
mode is entered. OPILR can only be read through the OnCE serial interface. This register
is affected by the operations performed during the debug mode and must be restored by
the external command controller when returning to normal mode. Since there is no direct
write access to this register, this task is accomplished in the first write to OPDBR after en-
tering the debug mode or after executing the GO command; the data from OPDBR is
transferred to OPILR only in these cases.
10.7.3 Global Data Bus Register (OGDBR)
The OGDBR is a 24-bit latch that can only be read through the OnCE serial interface.
OGDBR is not actually required from a pipeline status restore point of view but is required
as a means of passing information between the chip and the external command controller.
OGDBR is mapped on the X internal I/O space at address $FFFC. Whenever the external
command controller needs the contents of a register or memory location, it will force the
chip to execute an instruction that brings that information to OGDBR. Then, the contents
of OGDBR will be delivered serially to the external command controller by the command
"READ GDB REGISTER".
10.8
PROGRAM ADDRESS BUS HISTORY BUFFER
There are two read-only PAB registers which give pipeline information when the debug
mode is entered. The OPABFR register tells which opcode address is in the fetch stage
of the pipeline and OPABDR tells which opcode is in the decode stage. To ease debug-
ging activity and keep track of program flow, a First-In-First-Out (FIFO) buffer stores the
DSCK
DSI
DSO
Figure 10-8 OnCE Pipeline Information and GDB Registers
10- 18
GDB REGISTER (OGDBR)
PDB REGISTER (OPDBR)
PIL REGISTER (OPILR)
ON-CHIP EMULATION (OnCE)
GDB
PDB
PIL
MOTOROLA
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