Wait Processing State; Section 7.5 Wait Processing State; Wait Instruction Timing - Motorola DSP56000 Manual

24-bit digital signal processor
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7.5

WAIT PROCESSING STATE

The WAIT instruction brings the processor into the wait processing state which is one of
two low power-consumption states. Asserting the OnCE's debug request pin releases
the DSP from the wait state. In the wait state, the internal clock is disabled from all inter-
nal circuitry except the internal peripherals. All internal processing is halted until an
unmasked interrupt occurs, the Debug Request pin of the OnCE is asserted, or the DSP
is reset.
Figure 7-15 shows a WAIT instruction being fetched, decoded, and executed. It is
fetched as n3 in this example and, during decode, is recognized as a WAIT instruction.
The following instruction (n4) is aborted, and the internal clock is disabled from all inter-
nal circuitry except the internal peripherals. The processor stays in this state until an
interrupt or reset is recognized. The response time is variable due to the timing of the
interrupt with respect to the internal clock. Figure 7-15 shows the result of a fast interrupt
bringing the processor out of the wait state. The two appropriate interrupt vectors are
fetched and put in the instruction pipe. The next instruction fetched is n4, which had been
aborted earlier. Instruction execution proceeds normally from this point.
INTERRUPT CONTROL CYCLE 1
INTERRUPT CONTROL CYCLE 2
FETCH
DECODE
EXECUTE
INSTRUCTION CYCLE COUNT
i
= INTERRUPT
ii
= INTERRUPT INSTRUCTION WORD
n = NORMAL INSTRUCTION WORD
Figure 7-16 shows an example of the WAIT instruction being executed at the same time
that an interrupt is pending. Instruction n4 is aborted as before. The WAIT instruction
causes a five-instruction-cycle delay from the time it is decoded, after which the interrupt
is processed normally. The internal clocks are not turned off, and the net effect is that of
executing eight NOP instructions between the execution of n2 and ii1.
7 - 36
WAIT PROCESSING STATE
n3
n4
n2
WAIT
n1
n2
WAIT
1
2
3
Figure 7-15 Wait Instruction Timing
PROCESSING STATES
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
i
i
ii1
4
5
6
7
ONLY INTERNAL PERIPHERALS
RECEIVE CLOCK
ii2
n4
n5
ii1
ii2
n4
ii1
ii2
8
9
10
MOTOROLA

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