Three-Stage Pipeline - Motorola DSP56000 Manual

PROGRAM CONTROL UNIT (PCU) ARCHITECTURE
SERIAL EXECUTION OF INSTRUCTIONS
Instruction/Data Fetch
Instruction Decode
Instruction Execution
INSTRUCTION FETCH
INSTRUCTION DECODE
INSTRUCTION EXECUTION
PARALLEL INITIAL
OPERATIONS CONDITIONS
ADDRESS
UPDATE R0=$0005
(AGU) R4=$0008
A:
INSTRUCTION A2=$00
EXECUTION A1=$000066
A0=$000000
(DATA ALU) X0=$400000
Y1=$000077
X MEMORY DATA
AT ADDRESS
$0005 $000005
$0006 $000006
$0007 $000007
DATA
Y MEMORY
AT ADDRESS
$0008 $000008
$000009
$0009
MOTOROLA
EXAMPLE PROGRAM SEGMENT
Instruction 1 MACR X0,Y1,A
Instruction 2 CLR A
Instruction 3 MAC X0,Y1,A
SEQUENCE OF OPERATIONS
Instruction Cycle 2
Instruction Cycle 1
INSTRUCTION INSTRUCTION
FETCH FETCH
LOGIC LOGIC
1
INSTRUCTION
DECODE
LOGIC
EXECUTION OF EXAMPLE PROGRAM
Instruction Cycle 1 Instruction Cycle 2 Instruction Cycle 3 Instruction Cycle 4 Instruction Cycle 5
I1
Figure 5-3 Three-Stage Pipeline
PROGRAM CONTROL UNIT
X:(R0)+,X0 Y:(R4)+,Y1
X0,X:(R0)+ A,Y:(R4)-
X:(R0)+,X0 Y:(R4)+,Y1
Instruction Cycle 3 Instruction Cycle
INSTRUCTION
INSTRUCTION
FETCH
LOGIC
3
2
INSTRUCTION INSTRUCTION
DECODE
DECODE
LOGIC
2
1
INSTRUCTION
INSTRUCTION
EXECUTION
EXECUTION
LOGIC
1
I2 I3
I1 I2
I1
R0=5+1
R4=8+1
A:
A2=$00
A1=$0000A2
A0=$000000
X0=$000005
Y1=$000008
$000005
$000006
$000007
$000008
$000009
Instruction Cycle 5
INSTRUCTION
FETCH FETCH
LOGIC LOGIC
4
INSTRUCTION
DECODE
LOGIC LOGIC
3
INSTRUCTION
EXECUTION
LOGIC
2 LOGIC
3
I4 I5
I3 I4
I2 I3
R0=6+1 R0=7+1
R4=9–1 R4=8+1
A: A:
A2=$00 A2=$00
A1=$000000 A1=$000000
A0=$000000 A0=$000050
X0=$000005 X0=$000007
Y1=$000008 Y1=$000008
$000005 $000005
$000005 $000005
$000007 $000007
$000008 $000008
$0000A2 $0000A2
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