OnCE TRACE LOGIC
The trace counter allows more than one instruction to be executed in real time before the
chip returns to the debug mode of operation. This feature helps the software developer
debug sections of code which do not have a normal flow or are getting hung up in infinite
loops. The trace counter also enables the user to count the number of instructions exe-
cuted in a code segment.
To initiate the trace mode of operation, the counter is loaded with a value, the program
counter is set to the start location of the instruction(s) to be executed real-time, the TME
bit is set in the OSCR, and the processor exits the debug mode by executing the appro-
priate command issued by the external command controller.
Upon exiting the debug mode, the counter is decremented after each execution of an in-
struction. Interrupts are serviceable, and all instructions executed (including fast interrupt
services and the execution of each repeated instruction) will decrement the trace counter.
Upon decrementing the trace counter to zero, the processor will re-enter the debug mode,
the trace occurrence bit TO in the OSCR will be set, and the DSO pin will be toggled to
indicate that the processor has entered debug mode and is requesting service (ISTRACE
END OF INSTRUCTION
Figure 10-7 OnCE Trace Logic Block Diagram
10.5.1 Trace Counter (OTC)
The OTC is a 24-bit counter that can be read, written, or cleared through the OnCE serial
interface. If N instructions are to be executed before entering the debug mode, the Trace
Counter should be loaded with N-1. The Trace Counter is cleared by hardware reset.
ON-CHIP EMULATION (OnCE)
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